Kintex UltraScale KCU1500 Acceleration Development Board
30
UG1234 (v2017.1) June 20, 2017
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Chapter 3:
Hardware Platform
When a new partial bitstream is to be downloaded, the device driver writes to a
gate_pr
register that causes its output to do the following:
°
Hold the static base region reset controller
psreset_regslice_data_pr
in
reset, which issues a synchronous reset to the
regslice_data
AXI Register Slice
IP, and thereby holds the XDMA data path flop-flops at the boundary of the static
and reconfigurable regions in reset.
°
Hold the static base region reset controller
psreset_regslice_ctrl_pr
in
reset, which issues a synchronous reset to the
regslice_control
AXI Register
Slice IP, and thereby holds the XDMA control path flop-flops at the boundary of the
static and reconfigurable regions in reset.
°
Hold logic in the reconfigurable expanded region in reset by driving a reset source
signal to the reset controllers for synchronization of that region into the
appropriate clock domains.
After the new partial bitstream is downloaded and the accelerator device is ready to
operate with the new binary, the device driver clears the
gate_pr
register, causing
downstream reset assertions to be synchronously removed from the reconfigurable
expanded region and the static base region boundary flip-flops.
The following figure shows the
pr_isolation_expanded
static base region level of
sub-hierarchy.
X-Ref Target - Figure 3-16
Figure 3-16:
Partial Reconfiguration Support Logic in pr_isolation_expanded Sub-Hierarchy
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