Kintex UltraScale KCU1500 Acceleration Development Board
22
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 3:
Hardware Platform
• One AXI Interconnect instance is present per master interface,
M00_AXI
through
M03_AXI
.
Though providing 1x1 connectivity in the platform with training kernels, the SDAccel
System Compiler flow implements the user-defined connectivity from kernel(s) to
downstream SmartConnect instances and then to DDR4 memory, as defined in
Sparse
Memory Connectivity
. In general, the SDAccel System Compiler instantiates user kernels,
then the AXI Interconnect instances on slave and master sides of those kernels, and makes
all necessary connections to the pre-defined Programmable Region boundary. In this way,
although the contents of the Programmable Region depend on the user code, the necessary
connectivity to the platform is maintained.
Note:
The optional
KERNEL_CLK2
and
KERNEL_RESET2
ports are unused in the platform training
kernels, but are available to user RTL kernels as needed.
The SDAccel OpenCL Programmable Region IP instance customization Basic tab is shown in
the following figure.
X-Ref Target - Figure 3-10
Figure 3-10:
SDAccel OpenCL Programmable Region IP Customization - Basic Tab
Send Feedback
