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Kintex UltraScale KCU1500 Acceleration Development Board
31
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 4
Software Platform
Introduction
The Xilinx® Acceleration KCU1500 4DDR Expanded Partial Configuration platform is a
memory-mapped system with PCIe® host connectivity supported by a kernel mode DMA
driver for the XDMA IP. A hardware abstraction layer (HAL) driver isolates the SDAccel™
Software Platform runtime software from the implementation details of the
kernel mode
drivers, which interact
with the platform hardware based on a known address mapping.
This chapter provides the address map and the software layers for the design.
Address Map
The IP integrator block diagram specifies the following address map for the IP cores in the
reference design. The
xlcdma
driver defines these offsets in its header files.
Table 4-1:
Reference Design Address Map
Master IP Core AXI Master Interface
Slave IP Core
AXI Slave
Interface
Offset
Address
Range High Address
XDMA, through
dma_pf_demux
S_AXI_MGNTPF
AXI4-Lite control
interface for
Management
Physical Function
u_ocl_region
SDAccel
OpenCL
Programmable
Region
S_AXI
0x0000_0000
128K 0x0001_FFFF
axi_hwicap
AXI HWICAP for
partial
bitstream
download
S_AXI_LITE 0x0002_0000
64K
0x0002_FFFF
gate_pr
GPIO for partial
reconfiguration
isolation
S_AXI
0x0003_0000
4K
0x0003_0FFF
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