Kintex UltraScale KCU1500 Acceleration Development Board
19
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 3:
Hardware Platform
Contained within the
memc
sub-hierarchy of the reconfigurable expanded region as shown
in the following figure, the four DDR4 IP instances are individually accessed, and
individually indicate their calibration status using the
c0_init_calib_complete
output
port. The logical
AND
of these signals is available to the device driver using a
memory-mapped GPIO IP instance in the static base region.
As introduced in
Stacked Silicon Interconnect (SSI) Technology Support in Chapter 2
, the
ddrmem_0
and
ddrmem_1
instances are located in the lower SLR of the device, the
ddrmem_2
and
ddrmem_3
instances are located in the upper SLR.
AXI Clock Converter IP instances facilitate lower-speed SLR crossing of control signals by
converting from a 50 MHz clock domain source in the lower SLR into the DDR4 IP native 300
MHz AXI clock domain for those DDR4 IP instances in the upper SLR.
IMPORTANT:
An outcome of locating the DDR4 memory controllers in the reconfigurable region is that
DDR4 global memory content is lost when a new partial bitstream is downloaded.
X-Ref Target - Figure 3-7
Figure 3-7:
DDR4 IP Instances and Supporting IP in Reconfigurable Expanded Region memc
Sub-Hierarchy
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