Kintex UltraScale KCU1500 Acceleration Development Board
23
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 3:
Hardware Platform
The following figure shows the Advanced tab.
For more information on the Programmable Region, the IP that defines it, and the DSA
creation flow, see the
SDAccel Environment Platform Development Guide
(UG1164)
[Ref 2]
.
AXI Interconnectivity
The primary data path of the platform consists of AXI memory-mapped access from the
host (using an XDMA IP instance) to all global memory (using individual DDR4 IP instances),
and from the user kernels to user-defined regions of global memory. High-performance
data path connectivity is implemented using five instances of AXI SmartConnect IP, with the
topology previously described in
Sparse Memory Connectivity in Chapter 2
.
Contained within the interconnect sub-hierarchy of the reconfigurable expanded region as
shown in
Figure 3-12
, the five SmartConnect IP instances together provide both the host
and the user kernels with high-performance access to the four DDR4 IP memory controllers.
X-Ref Target - Figure 3-11
Figure 3-11:
SDAccel OpenCL Programmable Region IP Customization - Advanced Tab
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