SDAccel Platform
Reference Design
User Guide
Kintex UltraScale KCU1500
Acceleration Development
Board
UG1234 (v2017.1) June 20, 2017
Page 1: ...SDAccel Platform Reference Design User Guide Kintex UltraScale KCU1500 Acceleration Development Board UG1234 v2017 1 June 20 2017...
Page 2: ...te Version Revision 06 20 2017 2017 1 Updated to a new board platform Title changed from KU115 to KCU1500 Reference Design files updated to the 2017 1 SDAccel Environment and updated for the new platf...
Page 3: ...nvironment 10 Sparse Memory Connectivity 11 Stacked Silicon Interconnect SSI Technology Support 12 Chapter 3 Hardware Platform Introduction 14 Host Connectivity 16 Memory Control 18 SDAccel OpenCL Pro...
Page 4: ...Install Bring Up and Use Introduction 44 Installation 44 Bring Up Tests 46 Use with the SDAccel Environment 46 Appendix A Additional Resources and Legal Notices Xilinx Resources 50 Solution Centers 5...
Page 5: ...on flow described later in this document The DSA produced by this platform is available with the 2017 1 SDx Environments in the following file xilinx_kcu1500_4ddr xpr_4_0 dsa Though the platform is de...
Page 6: ...atform The SDAccel OpenCL Programmable Region IP core and its designated level of hierarchy enable the platform to be used with the SDAccel System Compiler C C OpenCL and RTL user kernels Partitioning...
Page 7: ...he reference design but are available with the SDx Environments installation and are described in Chapter 4 Software Platform For more details on software and device driver installation see the SDx En...
Page 8: ...rimarily the Xilinx DMA subsystem for PCI Express basic control interfaces and clock sources is contained within a static base region floorplanned to less than 8 of the device area that cannot be used...
Page 9: ...anded region logic is highlighted green In addition to the prominent rectangular regions of DDR4 memory controller IP instances the reconfigurable expanded region contains the placeholder add one kern...
Page 10: ...ilable to the Programmable Region with user kernels is the expanded region as described above Software compatibility The memory mapped IP cores including the SDAccel OpenCL Programmable Region IP core...
Page 11: ...the 16GB space However users can specify the required connectivity mapping of their kernels to master interfaces such that any kernel can access the amount of global memory it requires up to and inclu...
Page 12: ...High Performance I O banks they utilize The remaining two DDR4 SDRAM memory controller IP instances are floorplanned to the upper SLR in regions around the High Performance I O banks they utilize The...
Page 13: ...the Programmable Region are not floorplanned and can be placed on either side of the SLR as determined by the implementation tools Note The pipeline stages are actually submodules of SmartConnect IP...
Page 14: ...nnectivity Memory Control SDAccel OpenCL Programmable Region IP and the Programmable Region AXI Interconnectivity Application Profiling and Other Features Clocking and Reset The top level of the platf...
Page 15: ...0 2017 www xilinx com Chapter 3 Hardware Platform X Ref Target Figure 3 1 Figure 3 1 Top Level IP Integrator Block Diagram Default View with Interfaces and Wires X Ref Target Figure 3 2 Figure 3 2 Top...
Page 16: ...3 x8 connectivity or 8 0 GT s The Kintex UltraScale KCU1500 Acceleration development board supplies a 100 MHz reference clock and uses PCIe block location X0Y0 The platform uses an AXI memory mapped i...
Page 17: ...mory mapped platform resources over its AXI4 Lite control interface As shown in the following figure the XDMA IP is customized to use two DMA read and two DMA write channels with 32 read IDs and 16 wr...
Page 18: ...6HA 083E components on the Kintex UltraScale KCU1500 Acceleration development board with a 512 bit data width 32 bit address width AXI memory mapped interface providing high bandwidth platform fabric...
Page 19: ...Interconnect SSI Technology Support in Chapter 2 the ddrmem_0 and ddrmem_1 instances are located in the lower SLR of the device the ddrmem_2 and ddrmem_3 instances are located in the upper SLR AXI Cl...
Page 20: ...vity to the remainder of the platform As previously described in Expanded Partial Reconfiguration in Chapter 2 recall that although only the Programmable Region is replaced with user defined kernel co...
Page 21: ...n provides users the flexibility to run logic in RTL kernels at a different frequency than or generally asynchronous to the DATA_CLK and DATA_RESET domain IMPORTANT Data paths must be synchronous to t...
Page 22: ...Compiler instantiates user kernels then the AXI Interconnect instances on slave and master sides of those kernels and makes all necessary connections to the pre defined Programmable Region boundary I...
Page 23: ...ll global memory using individual DDR4 IP instances and from the user kernels to user defined regions of global memory High performance data path connectivity is implemented using five instances of AX...
Page 24: ...I Performance Monitor IP for application profiling support see Application Profiling and Other Features for details and is synchronous to the dedicated AXI Performance Monitor clock The interconnect_a...
Page 25: ...s and associated peripherals The management path driven by the dma_pf_demux S_AXI_MGNTPF interface provides the XDMA IP master with memory mapped access to peripherals in both the static base regions...
Page 26: ...protection of the static base region hardware against potential AXI protocol violations from kernels SDx Feature ROM to assist the SDAccel Software Platform in interpreting the Hardware Platform feat...
Page 27: ...Table 3 1 Platform Clock Domains Clock Domain Source Frequency Use in Platform XDMA XDMA IP core 250 MHz Within XDMA IP core and its AXI master interfaces AXI4 Lite control Clocking Wizard IP instance...
Page 28: ...Wizard IP instance using a PLL the kernel clock and kernel clock 2 are each generated from a separate memory mapped Clocking Wizard IP instance using an MMCM This is to support the automatic frequenc...
Page 29: ...of that instance The dcm_locked clock is stable input of a reset controller operating synchronously to the XDMA clock is driven by user_lnk_up output of the XDMA IP instance The ext_reset_n reset sou...
Page 30: ..._control AXI Register Slice IP and thereby holds the XDMA control path flop flops at the boundary of the static and reconfigurable regions in reset Hold logic in the reconfigurable expanded region in...
Page 31: ...apter provides the address map and the software layers for the design Address Map The IP integrator block diagram specifies the following address map for the IP cores in the reference design The xlcdm...
Page 32: ...axi_i2c I2C controller for Kintex UltraScale KCU1500 Acceleration Developer Board fan S_AXI 0x0004_1000 4K 0x0004_1FFF clkwiz_ kernel Clocking Wizard kernel clock source S_AXI_LITE 0x0005_0000 4K 0x0...
Page 33: ...linx Virtual Cable S_AXI 0x000C_0000 64K 0x000C_FFFF axi_firewall _ctrl AXI Firewall to protect Management Physical Function control path S_AXI_CTL 0x000D_0000 64K 0x000D_FFFF axi_firewall _ctrl_user...
Page 34: ...ocl_region SDAccel OpenCL Programmable Region S_AXI 0x0000_0000 128K 0x0001_FFFF feature_rom _ctrl AXI BRAM Controller for Feature ROM S_AXI 0x000B_0000 4K 0x000B_0FFF debug_bridge _xvc Debug Bridge f...
Page 35: ...e offload FIFO for application profiling S_AXI_ FULL 0x0000_0020 _ 0000_0000 4G 0x0000_0020_ FFFF_FFFF SDAccel OpenCL Programmable Region M00_AXI AXI memory mapped data interface ddrmem_0 DDR4 channel...
Page 36: ...SDx Environments installation and are developed for the specified address mapping and memory mapped IP functionality When the platform is implemented as a DSA and used with the SDAccel Environment th...
Page 37: ...the SDAccel runtime to communicate with the PCIe accelerator card It is used for downloading FPGA bitstreams allocating deallocating and migrating buffers device profiling and for communicating with...
Page 38: ...ructed and validated block diagram ready to synthesize run_synth tcl Synthesizes the IP cores of the design followed by the top level This script is to be run after create_design tcl run_impl tcl Impl...
Page 39: ...successfully completed Note If you do not want to create a DSA for the SDAccel Environment you can simply generate a bitstream after run_impl tcl completes following option 2 above but forgoing the u...
Page 40: ...ion with this version of Vivado Table 5 2 IP Repository Paths from create_design tcl Command Purpose set_property ip_repo_paths sourcesDir iprepo axi_perf_mon_v5_0 current_project Loads locally modifi...
Page 41: ...CONFIGURABLE true get_cells xcl_design_i expanded_region set_property dsa flash_interface_type spix8 current_project Sets the flash_interface_type field value in the DSA metadata set_property dsa desc...
Page 42: ...tacked Silicon Interconnect SSI Technology Support in Chapter 2 The following code snippet is an example create_pblock pblock_lower add_cells_to_pblock get_pblocks pblock_lower get_cells list xcl_desi...
Page 43: ...ctrl add_cells_to_pblock get_pblocks pblock_upper get_cells list xcl_design_i expanded_region memc axicc_ddrmem_3_ctrl add_cells_to_pblock get_pblocks pblock_upper get_cells list xcl_design_i expanded...
Page 44: ...affect compatibility with the host Kintex UltraScale KCU1500 Acceleration development board or the SDAccel System Compiler flow so confirming successful installation and bring up is important Installa...
Page 45: ...t operational status of the platform in more detail including the HAL driver version PCIe IDs global memory details FPGA temperature and voltage compute unit status and more use the xbsak utility incl...
Page 46: ...h build scripts the set of bring up tests exercise low level functionality of the accelerator device through their implementation as kernels in the SDAccel System Compiler flow download as partial bit...
Page 47: ...ified Connectivity The Programmable Region has four AXI memory mapped master interfaces each of which connect to one of the four DDR4 IP memory controllers As described in Sparse Memory Connectivity i...
Page 48: ...l clock 2 is identified by key 1 For example to specify that the kernel clock frequency should target 250 MHz rather than the default of 300 MHz and that kernel clock 2 should target 400 MHz rather th...
Page 49: ...lower frequency than intended As described in Expanded Partial Reconfiguration in Chapter 2 each compiler run places and routes user kernels together with the remainder of the logic in the reconfigura...
Page 50: ...cess to Xilinx documents videos and support resources which you can filter and search to find information To open the Xilinx Documentation Navigator DocNav From the Vivado IDE select Help Documentatio...
Page 51: ...or to notify you of updates to the Materials or to product specifications You may not reproduce modify distribute or publicly display the Materials without prior written consent Certain products are...
