XESS XStend XS40, Manual

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006- CONSTANT yes: STD_LOGIC := '1';
007- CONSTANT no: STD_LOGIC := '0';
008- CONSTANT ready: STD_LOGIC := '1';
009- CONSTANT overrun: STD_LOGIC := '1';
010- CONSTANT underrun: STD_LOGIC := '1';
011- CONSTANT left: STD_LOGIC := '0';
012- CONSTANT right: STD_LOGIC := '1';
013-
014- COMPONENT clkgen
015- GENERIC
016- (
017- ...
018- );
019- PORT
020- (
021- ...
022- );
023- END COMPONENT;
024-
025- COMPONENT channel
026- GENERIC
027- (
028- ...
029- );
030- PORT
031- (
032- ...
033- );
034- END COMPONENT;
035-
036- COMPONENT codec_intfc
037- GENERIC
038- (
039- ...
040- );
041- PORT
042- (
043- ...
044- );
045- END COMPONENT;
046- END PACKAGE;
Once the codec interface module is completed and packaged, we can use it in an
application. The simplest use is to have the FPLD accept the left and right stereo inputs
from the codec ADCs and loop these back to the codec DACs so they can output the
stereo signals.
The VHDL code for the loopback application is detailed in Listing 27 . The inputs and
outputs of the loopback design are as follows:
clk: This is the 12 MHz clock from the XS Board.
reset: A high level on this input synchronously resets the codec interface module. The
reset input is driven from the parallel port of the PC.