XESS XStend XS40, Manual

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ldac_in, rdac_in: The DAC shift registers are loaded in parallel with bits passed through
these inputs.
ladc_out_rdy, rdac_out_rdy: These outputs go high after all the bits have been shifted
from the codec into the left or right ADC shift register, respectively.
adc_overrun: This output goes high if new serial data is shifted into either the left or right
ADC shift register before the old contents have been read out through the parallel
outputs.
ldac_in_rdy, rdac_in_rdy: These outputs go high after all the bits in the left or right DAC
shift register have been shifted over to the codec, respectively.
dac_underrun: This output goes high if either the left or right DAC shift register starts
shifting data over to the codec before it has been written through the parallel inputs.
mclk: This output is the master clock for the codec chip.
sclk: This output is the clock for synchronizing serial data transfers between the FPLD
and the codec.
lrck: This output controls the activation of the left and right channel circuitry in the codec.
sdin: The serial data stream for the codec DAC is shifted out through this output.
sdout: The serial data stream from the codec ADC is shifted in through this input.
Within the main body of the top-level module architecture section, the following modules
are instantiated:
u0: One clock generator module is instantiated. It receives the 12 MHz clock as an input
and generates the master clock, left/right clock, and serial shift clock for the codec. It
also outputs the position of the current bit in the serial stream and the current cycle
within each bit period.
Lines 73—75: The input signals to the codec on the XStend V1.3 Board pass through
inverters. Therefore, the clock signals are inverted on these lines to remove the effect
of the inverters.
u_left: The module, which handles the left channel of the codec, is instantiated. This
module is activated during one half of the left/right clock period. It is selected for
reading or writing by the left/right selection input.
u_right: The module, which handles the right channel of the codec, is instantiated. This
module is activated during the other half of the left/right clock period. It is selected for
reading and writing by the opposite polarity of the left/right selection input.
Lines 133—134: The overrun and underrun error indicators for the total codec interface
are formed by the logical-OR of the associated error outputs of the left and right
channel modules. Thus an error is reported if either channel reports an error.
Line 138: The serial data stream that is transmitted to the codec chip is selected from the
output data stream of the currently-active channel module. The data stream input to