XESS XStend XS40, Manual

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the codec on the XStend V1.3 Board passes through an inverter. Therefore, the data
stream is inverted on this line to remove the effect of the inverter.
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Listing 25: VHDL code for the top-level codec interface module.
001- LIBRARY IEEE,codec;
002- USE IEEE.std_logic_1164.ALL;
003- USE IEEE.std_logic_unsigned.ALL;
004- USE codec.codec.ALL;
005-
006- ENTITY codec_intfc IS
007- GENERIC
008- (
009- DAC_WIDTH: positive := 20;
010- ADC_WIDTH: positive := 20;
011- CHANNEL_DURATION: positive := 128 -- must be 128
012- );
013- PORT
014- (
015- -- interface I/O signals
016- clk: IN std_logic; -- clock input
017- reset: IN std_logic; -- synchronous active-high reset
018- lrsel: IN std_logic; -- select L/R channel for read/write
019- rd: IN std_logic; -- read from the codec ADC
020- wr: IN std_logic; -- write to the codec DAC
021- ladc_out: OUT std_logic_vector(ADC_WIDTH-1 DOWNTO 0); -- L ADC
022- radc_out: OUT std_logic_vector(ADC_WIDTH-1 DOWNTO 0); -- R ADC
023- ldac_in: IN std_logic_vector(DAC_WIDTH-1 DOWNTO 0); -- left DAC
024- rdac_in: IN std_logic_vector(DAC_WIDTH-1 DOWNTO 0); -- right DAC
025- ladc_out_rdy: OUT std_logic; -- left ADC output ready to read
026- radc_out_rdy: OUT std_logic; -- right ADC output ready to read
027- adc_overrun: OUT std_logic; -- ADC overwritten before read
028- ldac_in_rdy: OUT std_logic; -- left DAC in ready to be written
029- rdac_in_rdy: OUT std_logic; --right DAC in ready to be written
030- dac_underrun: OUT std_logic; -- DAC did not receive data in time
031- -- codec chip I/O signals
032- mclk: OUT std_logic; -- master clock output to codec
033- sclk: OUT std_logic; -- serial data clock to codec
034- lrck: OUT std_logic; -- left/right codec channel select
035- sdin: OUT std_logic; -- serial output to codec DAC
036- sdout: IN std_logic -- serial input from codec ADC
037- );
038- END codec_intfc;
039-
040- ARCHITECTURE codec_intfc_arch OF codec_intfc IS
041- SIGNAL mclk_int: std_logic; -- internal codec master clock
042- SIGNAL lrck_int: std_logic; -- internal L/R codec channel select
043- SIGNAL sclk_int: std_logic; -- internal codec data shift clock
044- SIGNAL bit_cntr: std_logic_vector(5 DOWNTO 0);
045- SIGNAL subcycle_cntr: std_logic_vector(1 DOWNTO 0);
046- SIGNAL lsdin: std_logic;
047- SIGNAL rsdin: std_logic;
048- SIGNAL ladc_overrun: std_logic;