XESS XStend XS40, Manual

Page: 47 / 63

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070- (adc_full=YES AND adc_rd=YES)
071- ELSE NO;
072- read_adc:
073- PROCESS(clk,adc_rd_nxt)
074- BEGIN
075- IF(clk'event AND clk='1') THEN
076- IF(reset=YES) THEN
077- adc_rd <= NO;
078- ELSE
079- adc_rd <= adc_rd_nxt;
080- END IF;
081- END IF;
082- END PROCESS;
083- -- ADC data is ready if register is full and hasn't been read yet
084- adc_out_rdy_int <= YES WHEN adc_full=YES AND adc_rd=NO ELSE NO;
085- adc_out_rdy <= adc_out_rdy_int;
086-
087- -- detect and signal overwriting of data from the codec ADC channels
088- detect_adc_overrun:
089- PROCESS(clk,reset,bit_cntr,chan_on,adc_out_rdy_int)
090- BEGIN
091- IF(clk'event AND clk='1') THEN
092- IF(reset=YES) THEN
093- adc_overrun <= NO;
094- ELSIF(bit_cntr=1 AND chan_on=YES AND adc_out_rdy_int=YES) THEN
095- adc_overrun <= YES;
096- END IF;
097- END IF;
098- END PROCESS;
099-
100- -- transmits data to codec DAC
101- tx_dac:
102- PROCESS(clk,reset,chan_on,subcycle_cntr,bit_cntr,dac_shfreg)
103- BEGIN
104- IF(clk'event AND clk='1') THEN
105- IF(reset=YES) THEN
106- dac_shfreg <= (OTHERS=>'0');
107- dac_empty <= YES;
108- ELSIF(chan_sel=YES AND wr=YES) THEN
109- dac_shfreg <= dac_in;
110- ELSIF(chan_on=YES AND subcycle_cntr=2) THEN
111- IF(bit_cntr<DAC_WIDTH-1) THEN
112- dac_empty <= NO;
113- dac_shfreg <= dac_shfreg(DAC_WIDTH-2 DOWNTO 0) & '0';
114- ELSIF(bit_cntr=DAC_WIDTH-1) THEN
115- dac_empty <= YES;
116- dac_shfreg <= dac_shfreg(DAC_WIDTH-2 DOWNTO 0) & '0';
117- END IF;
118- END IF;
119- END IF;
120- END PROCESS;
121-
122- -- output the serial data to the SDIN pin of the codec DAC
123- sdin <= dac_shfreg(DAC_WIDTH-1) WHEN chan_on=YES ELSE '0';