XESS XStend XS40 Manual Download Page 29

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clk:

The input for the 12 MHz clock of the XS Board is declared here. This clock sets the

maximum rate at which pixels can be sent to the monitor. The time interval within
each line for transmitting viewable pixels is 25.17

s, so this VGA generator circuit can

only put a maximum of 25.17 ms

12 MHz = 302 pixels on each line. For purposes

of storing images in the RAM, it is convenient to reduce this to 256 pixels per line and
blank the remaining 46 pixels. Half of these blank pixels are placed before the 256
viewable pixels and half are placed after them on a line. This centers the viewable
pixels between the left and right edges of the monitor screen.

reset:

This line declares an input, which will reset all the other circuitry to a known state.

hsyncb, vsyncb:

The outputs for the horizontal and vertical sync pulses are declared.

The hsyncb output is declared as a buffer because it will also be referenced within the
architecture section as a clock for the vertical line counter.

rgb:

The outputs that control the red, green, and blue color guns of the monitor are

declared here. Each gun is controlled by two bits, so there are four possible
intensities for each color. Thus, this circuit can produce 4

4 = 64 different colors.

address, data

: These lines declare the outputs for driving the address lines of the RAM

and the inputs for receiving the data from the RAM.

ceb, oeb, web

: These are the declarations for the outputs which drive the chip-select,

output-enable, and write-enable control lines of the RAM.

The preamble of the architecture section declares the following resources:

hcnt, vcnt

: The counters that store the current horizontal position within a line of pixels

and the vertical position of the line on the screen are declared on these lines. We will
call these the horizontal or pixel counter, and the vertical or line counter, respectively.
The line period is 31.77

s that is 381 clock cycles, so the pixel counter needs at least

nine bits of resolution. Each frame is composed of 528 video lines (only 480 are
visible, the other 48 are blanked), so a ten bit counter is needed for the line counter.

pixrg

: This is the declaration for the eight-bit register that stores the four pixels received

from the RAM.

blank, pblank

: This line declares the video blanking signal and its registered counterpart

that is used in the next pipeline stage.

Within the main body of the architecture section, these following processes are executed:

inc_horiz_pixel_counter:

This process describes the operation of the horizontal pixel

counter. The counter is asynchronously set to zero when the reset input is high. The
counter increments on the rising edge of each pixel clock. The range for the horizontal
pixel counter is [0,380]. When the counter reaches 380, it rolls over to zero on the
next cycle. Thus, the counter has a period of 381 pixel clocks. With a pixel clock of
12 MHz, this translates to a period of 31.75

inc_vert_line_counter:

This process describes the operation of the vertical line counter.

The counter is asynchronously set to zero when the reset input is high. The counter
increments on the rising edge of the horizontal sync pulse after a line of pixels is
completed. The range for the horizontal pixel counter is [0,527]. When the counter