XESS XStend XS40, Manual

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103- );
104-
105- rchan_sel <= YES WHEN lrsel=RIGHT ELSE NO;
106- rchan_on <= YES WHEN lrck_int=RIGHT ELSE NO;
107- u_right: channel
108- GENERIC MAP
109- (
110- DAC_WIDTH=>DAC_WIDTH,
111- ADC_WIDTH=>ADC_WIDTH
112- )
113- PORT MAP
114- (
115- clk=>clk,
116- reset=>reset,
117- chan_on=>rchan_on,
118- bit_cntr=>bit_cntr,
119- subcycle_cntr=>subcycle_cntr,
120- chan_sel=>rchan_sel,
121- rd=>rd,
122- wr=>wr,
123- adc_out=>radc_out,
124- dac_in=>rdac_in,
125- adc_out_rdy=>radc_out_rdy,
126- adc_overrun=>radc_overrun,
127- dac_in_rdy=>rdac_in_rdy,
128- dac_underrun=>rdac_underrun,
129- sdin=>rsdin,
130- sdout=>sdout
131- );
132-
133- dac_underrun <= YES WHEN ldac_underrun=YES OR rdac_underrun=YES
134- ELSE NO;
135- adc_overrun <= YES WHEN ladc_overrun=YES OR radc_overrun=YES
136- ELSE NO;
137-
138- -- generates the serial data output to the SDIN pin of the
139- -- codec DAC depending on which channel is being loaded
140- sdin <= NOT(lsdin) WHEN lrck_int=LEFT ELSE NOT(rsdin);
141-
142- END codec_intfc_arch;
The interfaces to these three modules are placed into the package shown in Listing 26 .
(The I/O declarations in the COMPONENT constructs have been removed for the sake of
brevity.) The declarations for the constants used in these modules are also included in the
package.
•
Listing 26 : VHDL code for the codec package.
001- LIBRARY IEEE;
002- USE IEEE.STD_LOGIC_1164.ALL;
003- USE IEEE.std_logic_unsigned.ALL;
004-
005- PACKAGE codec IS