XESS XStend XS40 Manual Download Page 19

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Table 4:

Connections between the XS40 Board and the XStend Board resources.

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XS40 Pin

(J1,J3,J18)

Power/ GND

DIP Switch

Push-buttons

LEDs

VGA

Interface

PS/2

Interface

RAMs

Stereo Codec

8051 uC

PC Parallel

Port

Oscillator

Function

UW-FPGA

BOARD Pin

2 +5V

+5V power source

LSB0

Left LED segment; RAM address line

P35

LSB1

Left LED segment; RAM address line

P36

LSB2

Left LED segment; RAM address line

P29

DIPSW4

Summary of Contents for XStend XS40

Page 1: ...ATE 7 5 1999 XStend Board V1 3 Manual XStend Board V1 3 Manual How to install and use your new XStend Board 2608 Sweetgum Drive Apex NC 27502 Toll free 800 549 9377 International 919 387 0076 FAX 919...

Page 2: ...sion Subject to the limitations specified above your sole and exclusive warranty shall be during the period of warranty specified above and at XESS s option the repair or replacement of the product Th...

Page 3: ...c 12 XILINX Xchecker Interface 13 Prototyping Area 13 Daughterboard Connector 14 Displaying Switch Settings on the XStend Board LEDs 20 Displaying Graphics from RAM Through the VGA Interface 23 VGA Co...

Page 4: ...com or check our web site at http www xess com FPGA n If you can t get your XILINX software tools installed properly send an e mail message describing your problem to hotline xilinx com or check thei...

Page 5: ...itor interface PS 2 keyboard mouse interface and static RAM let the XS Boards be used in video and computing experiments n The stereo codec and dual channel analog input output circuitry are useful fo...

Page 6: ...5 n a 42 2 header connector for add on daughterboards These resources are shown in the simplified view of the XStend Board Figure 1 Each of these resources will be described below...

Page 7: ...rds with 3 3V FPGAs will supply both 3 3V and 5V to the XStend Board while XS40 Boards with 5V FPGAs and XS95 Boards will supply only 5V Warning Version 1 0 of the XS40 Board with a 3 3V XC4000XL FPGA...

Page 8: ...nections from the XS40 and XS95 Boards to the LEDs on the XStend Board expressed as UCF constraints for the UCF syntax and usage tips check out http www xilinx com techdocs 2449 htm Listing 1 Connecti...

Page 9: ...used to initiate the programming of the XS40 Board It is not intended to be a general purpose input When closed or ON each DIP switch pulls the connected pin of the XS Board to ground When the DIP sw...

Page 10: ...2 and higher of the XS Boards already have their own VGA interfaces so the XStend circuitry is redundant for them The XS Board can drive the active low horizontal and vertical sync signals that contr...

Page 11: ...ons between the XStend PS 2 interface and the XS40 PS 2 KEYBOARD CONNECTIONS NET KB_CLK LOC P68 NET KB_DATA LOC P69 Listing 8 Connections between the XStend PS 2 interface and the XS95 PS 2 KEYBOARD C...

Page 12: ...R RIGHT XSTEND RAM Listing 10 Connections between the XStend RAMs and the XS95 NET D 0 LOC P44 DATA BUS NET D 1 LOC P43 NET D 2 LOC P41 NET D 3 LOC P40 NET D 4 LOC P39 NET D 5 LOC P37 NET D 6 LOC P36...

Page 13: ...NET LRCK LOC P66 LEFT RIGHT CODEC CHANNEL SELECT NET SCLK LOC P77 SERIAL DATA CLOCK NET SDOUT LOC P6 SERIAL DATA OUTPUT FROM CODEC NET SDIN LOC P70 SERIAL DATA INPUT TO CODEC NET CCLK LOC P44 CONTROL...

Page 14: ...the serial EPROM from socket U7 The connections between the Xchecker cable and the XS40 Board is listed in Table 3 Table 3 Connections between the XStend Board Xchecker interface and the XS40 Board Xc...

Page 15: ...ade through connector J3 The arrangement of pins on this connector exactly matches the arrangement of pins on the XS40 Board For example the pin at the bottom left of J3 on the XStend Board correspond...

Page 16: ...re connections For example the codec DIP switch and microcontroller port P1 are all connected to the same set of pins on the FPGA or CPLD So any design has to ensure that only one of these resources i...

Page 17: ...16 Figure 5 Programmer s model of the XS40 XStend Board combination...

Page 18: ...17...

Page 19: ...Switch Push buttons LEDs VGA Interface PS 2 Interface RAMs Stereo Codec 8051 uC PC Parallel Port Oscillator Function UW FPGA BOARD Pin 2 5V 5V power source 3 LSB0 A0 Left LED segment RAM address line...

Page 20: ......

Page 21: ...nts on jumpers J4 J7 and J8 of the XStend Board to enable the LED displays Remove the shunt on jumper J17 to keep the XStend codec serial output from interfering with the DIP switch logic levels n Dow...

Page 22: ...all RAMs 017 rst OUT STD_LOGIC microcontroller reset 018 019 END switches 020 021 ARCHITECTURE switches_arch OF switches IS 022 BEGIN 023 this prevents accidental activation of the RAMs or uC 024 oeb...

Page 23: ...0 016 net dipsw 7 loc p66 017 net dipsw 8 loc p69 018 net spareb loc p67 SPARE pushbutton input 019 net resetb loc p37 RESET pushbutton input 020 net lsb 0 loc p3 XStend left led digit segments 021 ne...

Page 24: ...segments 029 net rsb 1 loc p56 030 net rsb 2 loc p54 031 net rsb 3 loc p55 032 net rsb 4 loc p53 033 net rsb 5 loc p57 034 net rsb 6 loc p61 035 net rsb 7 loc p34 036 net db 1 loc p44 XStend bargraph...

Page 25: ...r input can be set to one of four levels by two digital outputs using a simple two bit digital to analog converter see Figure 7 The four possible levels on each analog input are combined by the monito...

Page 26: ...the top and bottom edges of the visible monitor screen The lines are sent to the monitor within a 15 25 ms window The vertical sync signal drops low a minimum of 0 45 ms after the last line and stays...

Page 27: ...he next iteration of the loop Since it has only two bits each pixel can store one of four colors The mapping from the two bit pixel value to the actual values required by the monitor electronics is do...

Page 28: ...ta from the RAM blanking signal and sync pulses are latched at the end of this stage so they can be used in the next stage Stage 2 The circuit uses the pixel data and the blanking signal to determine...

Page 29: ...of the architecture section declares the following resources hcnt vcnt The counters that store the current horizontal position within a line of pixels and the vertical position of the line on the scr...

Page 30: ...494 31 75 s 15 68 ms after the beginning of the first video line Line 91 This line describes the computation of the combinatorial blanking signal The video is blanked after 256 pixels on a line are d...

Page 31: ......

Page 32: ...t_hsyncb 1 063 ELSIF clk EVENT AND clk 1 THEN 064 IF hcnt 291 AND hcnt 337 THEN 065 horiz sync is low in this interval to signal start of new line 066 int_hsyncb 0 067 ELSE 068 int_hsyncb 1 069 END IF...

Page 33: ......

Page 34: ...40 005 net data 2 loc p39 006 net data 3 loc p38 007 net data 4 loc p35 008 net data 5 loc p81 009 net data 6 loc p80 010 net data 7 loc p10 011 net address 0 loc p3 012 net address 1 loc p4 013 net a...

Page 35: ...024 net address 13 loc p57 025 net address 14 loc p61 026 net ceb loc p65 027 net web loc p63 028 net oeb loc p62 029 net rgb 0 loc p21 030 net rgb 1 loc p23 031 net rgb 2 loc p19 032 net rgb 3 loc p1...

Page 36: ...VGA95 SVF file and a video test pattern into the XS95 XStend combination with the command XSLOAD TESTPATT HEX VGA95 SVF n Release the reset to the VGA circuitry with the command XSPORT 0 n Observe the...

Page 37: ...ese chips cannot interfere while receiving data from the keyboard Lines 25 26 The keyboard clock passes through an input buffer and then a global clock buffer before it reaches the rest of the circuit...

Page 38: ...40 BIT file into the XS40 XStend combination with the command XSLOAD KEYBRD40 BIT n Press keys on the keyboard and observe the results on the LED displays n The steps for compiling and testing the des...

Page 39: ...r 029 on the falling edge of the keyboard clock 030 gather_scancode 031 PROCESS buf_clk1 scancode 032 BEGIN 033 IF buf_clk1 EVENT AND buf_clk1 0 THEN 034 scancode kb_data scancode 9 DOWNTO 1 035 END I...

Page 40: ...7 loc p36 019 net db 8 loc p35 Inputting and Outputting Stereo Signals Through the Codec The stereo codec on the XStend Board is capable of digitizing two analog signals to 20 bits of resolution while...

Page 41: ......

Page 42: ...rial data shift clock is one quarter of the master clock So transmitting or receiving a 20 bit value will require 4 20 80 clock periods and this will fit within the shortest possible channel duration...

Page 43: ...ubcycle_cntr seq 1 DOWNTO 0 050 END clkgen_arch The VHDL code for the channel module is shown in Listing 24 The inputs and outputs of the clock generator as defined in the entity declaration are as fo...

Page 44: ...ll the bits from the ADC Once the reset is removed and the channel is active bits are shifted into the register during the third subcycle of each bit period the subcycles are numbered 0 1 2 and 3 Acce...

Page 45: ...aintained that indicates whether the DAC shift register has been written The flag is set when the DAC register for the channel is empty and it is selected for a write operation The flag will stay set...

Page 46: ...register is empty 038 SIGNAL dac_wr std_logic the DAC channel has been written 039 SIGNAL dac_wr_nxt std_logic the DAC channel has been written 040 SIGNAL dac_in_rdy_int std_logic internal version of...

Page 47: ...un NO 094 ELSIF bit_cntr 1 AND chan_on YES AND adc_out_rdy_int YES THEN 095 adc_overrun YES 096 END IF 097 END IF 098 END PROCESS 099 100 transmits data to codec DAC 101 tx_dac 102 PROCESS clk reset c...

Page 48: ...bit_cntr 1 AND chan_on YES AND dac_in_rdy_int YES THEN 152 dac_underrun YES 153 END IF 154 END IF 155 END PROCESS 156 END channel_arch The VHDL code for the top level module that combines the clock g...

Page 49: ...e architecture section the following modules are instantiated u0 One clock generator module is instantiated It receives the 12 MHz clock as an input and generates the master clock left right clock and...

Page 50: ...ogic_vector DAC_WIDTH 1 DOWNTO 0 right DAC 025 ladc_out_rdy OUT std_logic left ADC output ready to read 026 radc_out_rdy OUT std_logic right ADC output ready to read 027 adc_overrun OUT std_logic ADC...

Page 51: ...ntr subcycle_cntr 072 073 lrck NOT lrck_int invert for inverter in XStend V1 3 074 mclk NOT mclk_int 075 sclk NOT sclk_int 076 077 lchan_sel YES WHEN lrsel LEFT ELSE NO 078 lchan_on YES WHEN lrck_int...

Page 52: ...rrun YES WHEN ldac_underrun YES OR rdac_underrun YES 134 ELSE NO 135 adc_overrun YES WHEN ladc_overrun YES OR radc_overrun YES 136 ELSE NO 137 138 generates the serial data output to the SDIN pin of t...

Page 53: ...039 040 041 PORT 042 043 044 045 END COMPONENT 046 END PACKAGE Once the codec interface module is completed and packaged we can use it in an application The simplest use is to have the FPLD accept the...

Page 54: ...d the read and write control lines are asserted This reads the data from the ADC shift register and writes it into the DAC shift register during a single clock cycle Then the ADC and DAC registers wil...

Page 55: ...errun and overrun 052 adc_overrun s 1 error indicators to LEDs 053 054 055 loop PROCESS ldac_in_rdy ladc_out_rdy rdac_in_rdy radc_out_rdy 056 BEGIN 057 IF ladc_out_rdy yes AND ldac_in_rdy yes THEN 058...

Page 56: ...from jumpers J4 J7 and J8 to disable the LEDs Place a shunt on jumper J17 so the codec serial output data stream can reach the FPLD Set all the DIP switches to the OPEN position n Connect a stereo au...

Page 57: ...the OPEN position n Connect a stereo audio source such as a CD player to jack J9 Then plug a set of stereo mini headphones into jack J10 n Download the LOOP95 BIT file into the XS95 XStend combinatio...

Page 58: ...Appendix A XStend Schematics...

Page 59: ...XStend V1 3 XS Board Connectors...

Page 60: ...XStend V1 3 RAM...

Page 61: ......

Page 62: ...XStend V1 3 Stereo Codec...

Page 63: ......

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