XESS XStend XS40, Manual

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035- net hsyncb loc=p19;
036- net vsyncb loc=p67;
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Listing 19: XS95 UCF file for the VGA signal generator.
001- net clk loc=p9;
002- net reset loc=p46;
003- net data<0> loc=p44;
004- net data<1> loc=p43;
005- net data<2> loc=p41;
006- net data<3> loc=p40;
007- net data<4> loc=p39;
008- net data<5> loc=p37;
009- net data<6> loc=p36;
010- net data<7> loc=p35;
011- net address<0> loc=p75;
012- net address<1> loc=p79;
013- net address<2> loc=p82;
014- net address<3> loc=p84;
015- net address<4> loc=p1;
016- net address<5> loc=p3;
017- net address<6> loc=p83;
018- net address<7> loc=p2;
019- net address<8> loc=p58;
020- net address<9> loc=p56;
021- net address<10> loc=p54;
022- net address<11> loc=p55;
023- net address<12> loc=p53;
024- net address<13> loc=p57;
025- net address<14> loc=p61;
026- net ceb loc=p65;
027- net web loc=p63;
028- net oeb loc=p62;
029- net rgb<0> loc=p21;
030- net rgb<1> loc=p23;
031- net rgb<2> loc=p19;
032- net rgb<3> loc=p17;
033- net rgb<4> loc=p18;
034- net rgb<5> loc=p14;
035- net hsyncb loc=p15;
036- net vsyncb loc=p24;
The steps for compiling and testing the VGA design using an XS40 combined with an
XStend Board are as follows:
n Synthesize the VHDL code in the VGA40\VGA.VHD file for an XC4005XL FPGA.
n
Compile the synthesized netlist using the VGA40.UCF constraint file ( Listing 18 ).
n Mount an XS40 Board in the XStend Board and attach the downloading cable from
the XS40 to the PC parallel port. Apply 9VDC though jack J9 of the XS40. Place
shunts on jumpers J4, J7, and J8 of the XStend Board to enable the LED displays.
Remove the shunt on jumper J17 to keep the XStend codec serial output from