41
lrck:
This output controls the activation of the left and right channel circuitry in the codec
and the FPLD.
bit_cntr:
These outputs indicate the current bit being transmitted and received in the serial
data streams.
subcycle_cntr:
The duration of each serial data bit is divided into four phases and these
outputs indicate the current phase.
Within the main body of the clock generator architecture section, these operations occur:
gen_clock:
This process increments the sequencing counter and toggles the left/right
channel selector when the count reaches the duration for which a channel is active.
The codec chip requires that the channel duration be either 128, 192, or 256 master
clock periods in length. Thus, the total time to handle both channels is 256, 384, or
512 clock periods. This sets the sampling rate. So using a channel duration of 128
with a 12 MHz clock gives a sampling rate of 46.875 KHz that is sufficient for audio.
Lines 45
-47: The various clocks are output on these lines. The master clock and left/right
selector have already been discussed. The serial data shift clock is one-quarter of the
master clock. So transmitting or receiving a 20-bit value will require 4
×
20 = 80 clock
periods, and this will fit within the shortest possible channel duration.
Line 48
: The position of the current data bit in the serial stream for a channel is output
here. Since each bit has a duration of four clock periods, the position of the bit in the
stream is just the sequence counter with the two least-significant bits removed.
Line 49
: The position within a bit is output on this line. This is given by the two least-
significant bits of the sequence counter.
•
Listing 23:
VHDL code for the codec clock generator module.
001- LIBRARY IEEE,codec;
002- USE IEEE.std_logic_1164.ALL;
003- USE IEEE.std_logic_unsigned.ALL;
004- USE codec.codec.ALL;
005-
006- ENTITY clkgen IS
007- GENERIC
008- (
009- CHANNEL_DURATION: positive := 128 -- must be 128
010- );
011- PORT
012- (
013- -- interface I/O signals
014- clk: IN std_logic; -- clock input
015- reset: IN std_logic; -- synchronous active-high reset
016- -- codec chip clock signals
017- mclk: OUT std_logic; -- master clock output to codec
018- sclk: OUT std_logic; -- serial data clock to codec
019- lrck: OUT std_logic; -- left/right codec channel select
020- bit_cntr: OUT std_logic_vector(5 DOWNTO 0);
021- subcycle_cntr: OUT std_logic_vector(1 DOWNTO 0)
Summary of Contents for XStend XS40
Page 17: ...16 Figure 5 Programmer s model of the XS40 XStend Board combination...
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Page 58: ...Appendix A XStend Schematics...
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