XESS XStend XS40, Manual

Page: 55 / 63

54
026- GENERIC MAP
027- (
028- adc_width=>20,
029- dac_width=>20
030- )
031- PORT MAP
032- (
033- clk=>clk,
034- reset=>rst,
035- mclk=>mclk,
036- sclk=>sclk,
037- lrck=>lrck,
038- sdout=>sdout,
039- sdin=>sdin,
040- lrsel=>lrsel,
041- rd=>rd,
042- wr=>wr,
043- ladc_out=>left_channel, -- loop the left channel ADC
044- ldac_in=>left_channel, -- to the left channel DAC
045- radc_out=>right_channel, -- loop the right channel ADC
046- rdac_in=>right_channel, -- to the right channel DAC
047- ladc_out_rdy=>ladc_out_rdy,
048- radc_out_rdy=>radc_out_rdy,
049- ldac_in_rdy=>ldac_in_rdy,
050- rdac_in_rdy=>rdac_in_rdy,
051- dac_underrun=>s(0), -- connect underrun and overrun
052- adc_overrun=>s(1) -- error indicators to LEDs
053- );
054-
055- loop: PROCESS(ldac_in_rdy,ladc_out_rdy,rdac_in_rdy,radc_out_rdy)
056- BEGIN
057- IF(ladc_out_rdy=yes AND ldac_in_rdy=yes) THEN
058- lrsel<=left; -- loopback the left channel
059- rd<=yes; -- assert the read and
060- wr<=yes; -- write control signals
061- ELSIF(radc_out_rdy=yes AND rdac_in_rdy=yes) THEN
062- lrsel<=right; -- loopback the right channel
063- rd<=yes; -- assert the read and
064- wr<=yes; -- write control signals
065- ELSE
066- lrsel<=left; -- default channel selection
067- rd<=no; -- but don’t read or
068- wr<=no; -- write the registers
069- END IF;
070- END PROCESS;
071- END loopback_arch;
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Listing 28: XS40 UCF file for the stereo signal loopback application.
001- net clk loc=p13;
002- net rst loc=p44;
003- net sdout loc=p6;
004- net mclk loc=p9;