XESS XStend XS40, Manual

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/* pulse the vertical sync at the right time */
if vert_blank_cnt > VB0 and vert_blank_cnt < VB1
vsync = 0
else
vsync = 1
vert_blank_cnt = vert_blank_cnt + 1
/* go back to start of picture in RAM */
address = 0
Figure 9 shows how to pipeline certain operations to account for delays in accessing data
from the RAM. The pipeline has three stages:
Stage 1: The circuit uses the horizontal and vertical counters to compute the address
where the next pixel is found in RAM. The counters are also used to determine the
firing of the sync pulses and whether the video should be blanked. The pixel data
from the RAM, blanking signal, and sync pulses are latched at the end of this stage so
they can be used in the next stage.
Stage 2: The circuit uses the pixel data and the blanking signal to determine the binary
color outputs. These outputs are latched at the end of this stage.
Stage 3: The binary color outputs are applied to the DAC, which sets the intensity levels
for the monitor’s color guns. The actual pixel is painted on the screen during this
stage.
•
Figure 9: Pipelining of VGA signal generation tasks.
VGA Signal Generator in VHDL
The pseudocode and pipeline timing in the last section will help us to understand the
VHDL code for a VGA signal generator shown in
Listing 17 . The inputs and outputs of
the circuit as defined in the entity declaration are as follows: