XESS XStend XS40, Manual

Page: 51 / 63

50
049- SIGNAL radc_overrun: std_logic;
050- SIGNAL ldac_underrun: std_logic;
051- SIGNAL rdac_underrun: std_logic;
052- SIGNAL lchan_sel: std_logic;
053- SIGNAL rchan_sel: std_logic;
054- SIGNAL lchan_on: std_logic;
055- SIGNAL rchan_on: std_logic;
056- BEGIN
057-
058- u0: clkgen
059- GENERIC MAP
060- (
061- CHANNEL_DURATION=>CHANNEL_DURATION
062- )
063- PORT MAP
064- (
065- clk=>clk,
066- reset=>reset,
067- mclk=>mclk_int,
068- sclk=>sclk_int,
069- lrck=>lrck_int,
070- bit_cntr=>bit_cntr,
071- subcycle_cntr=>subcycle_cntr
072- );
073- lrck <= NOT(lrck_int); -- invert for inverter in XStend V1.3
074- mclk <= NOT(mclk_int);
075- sclk <= NOT(sclk_int);
076-
077- lchan_sel <= YES WHEN lrsel=LEFT ELSE NO;
078- lchan_on <= YES WHEN lrck_int=LEFT ELSE NO;
079- u_left: channel
080- GENERIC MAP
081- (
082- DAC_WIDTH=>DAC_WIDTH,
083- ADC_WIDTH=>ADC_WIDTH
084- )
085- PORT MAP
086- (
087- clk=>clk,
088- reset=>reset,
089- chan_on=>lchan_on,
090- bit_cntr=>bit_cntr,
091- subcycle_cntr=>subcycle_cntr,
092- chan_sel=>lchan_sel,
093- rd=>rd,
094- wr=>wr,
095- adc_out=>ladc_out,
096- dac_in=>ldac_in,
097- adc_out_rdy=>ladc_out_rdy,
098- adc_overrun=>ladc_overrun,
099- dac_in_rdy=>ldac_in_rdy,
100- dac_underrun=>ldac_underrun,
101- sdin=>lsdin,
102- sdout=>sdout