XESS XStend XS40, Manual

Page: 43 / 63

42
022- );
023- END clkgen;
024-
025- ARCHITECTURE clkgen_arch OF clkgen IS
026- SIGNAL lrck_int: std_logic;
027- SIGNAL seq: std_logic_vector(7 DOWNTO 0);
028- BEGIN
029- gen_clock:
030- PROCESS(clk,seq,lrck_int)
031- BEGIN
032- IF (clk'event AND clk='1') THEN
033- IF(reset=YES) THEN -- synchronous reset
034- seq <= (OTHERS=>'0');
035- lrck_int <= LEFT; -- start with left channel of codec
036- ELSIF(seq=CHANNEL_DURATION-1) THEN
037- seq <= (OTHERS=>'0'); -- reset sequencer every channel period
038- lrck_int <= NOT(lrck_int); -- toggle channel sel every period
039- ELSE
040- seq <= seq+1;
041- lrck_int <= lrck_int;
042- END IF;
043- END IF;
044- END PROCESS;
045- lrck <= lrck_int; -- output the channel selector to the codec
046- mclk <= clk; -- codec master clock equals input clock
047- sclk <= seq(1); -- serial data shift clock = 1/4 master clock
048- bit_cntr <= seq(7 DOWNTO 2);
049- subcycle_cntr <= seq(1 DOWNTO 0);
050- END clkgen_arch;
The VHDL code for the channel module is shown in Listing 24 . The inputs and outputs of
the clock generator as defined in the entity declaration are as follows:
clk: This is the main clock input, which is typically the 12 MHz clock from the XS Board.
reset: This input synchronously resets the channel.
chan_on: A high level on this input activates the channel. This input is usually controlled
by the left/right channel selector.
bit_cntr: These inputs inform the channel of the index of the serial data bit currently being
transmitted and received.
chan_sel: A high level on this input enables the interface that lets the shift registers be
read and written. (Note that despite its name, this input is not controlled by the
left/right channel selector.)
rd: A high level on this input outputs the value stored in the shift register connected to the
ADC.
wr: A high level on this input writes a new value into the shift register connected to the
DAC.