XESS XStend XS40, Manual

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interfering with the DIP switch logic levels. Set all the DIP switches to the OPEN
position.
n Attach a VGA monitor to the DB-HD15 connector (J5).
n Download the VGA40.BIT file and a video test pattern into the XS40/XStend
combination with the command:
XSLOAD TESTPATT.HEX VGA40.BIT
.
n Release the reset to the VGA circuitry with the command:
XSPORT 0
.
n Observe the color bars on the monitor screen.
n The steps for compiling and testing the design using an XS95 combined with an
XStend Board are as follows:
n Synthesize the VHDL code in the VGA95\VGA.VHD file for an XC95108 CPLD.
n Compile the synthesized netlist using the VGA95.UCF constraint file ( Listing 19 ).
n Generate an SVF file for the design.
n Mount an XS95 Board in the XStend Board and attach the downloading cable from
the XS95 to the PC parallel port. Apply 9VDC though jack J9 of the XS40. Place
shunts on jumpers J4, J7, and J8 of the XStend Board to enable the LED displays.
Remove the shunt on jumper J17 to keep the XStend codec serial output from
interfering. Set all the DIP switches to the OPEN position.
n Attach a VGA monitor to the DB-HD15 connector (J5).
n Download the VGA95.SVF file and a video test pattern into the XS95/XStend
combination with the command:
XSLOAD TESTPATT.HEX VGA95.SVF
.
n Release the reset to the VGA circuitry with the command:
XSPORT 0
.
n Observe the color bars on the monitor screen.
Reading Keyboard Scan Codes Through the PS/2 Interface
This example creates a circuit that accepts scan codes from a keyboard attached to the
PS/2 interface of the XStend Board. The binary pattern of the scan code is displayed on
the bargraph LEDs. In addition, if a scan code for one of the keys '0'—'9' arrives, then the
numeral will be displayed on the right LED display of the XStend Board.
The format of the scan code transmissions from the keyboard are shown in Figure 10 .
The keyboard electronics drive the clock and data lines. The start of a scan code
transmission is indicated by a low level on the data line on the falling edge of the clock.
The eight bits of the scan code follow (starting with the least-significant bit) on successive
falling clock edges. These are followed by an odd-parity bit and then a high-level stop bit.
When the clock line goes high after the stop bit, the receiver (in this case, the FPGA or
CPLD on the XS Board inserted in the XStend Board) can pull the clock line low to inhibit
any further transmissions. After the clock line is released and it returns to a high level, the