XESS XStend XS40, Manual

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016- reset: IN std_logic; -- synchronous active-high reset
017- chan_on: IN std_logic;
018- bit_cntr: IN std_logic_vector(5 DOWNTO 0);
019- subcycle_cntr: IN std_logic_vector(1 DOWNTO 0);
020- chan_sel: IN std_logic; -- select L/R channel for read/write
021- rd: IN std_logic; -- read from the codec ADC
022- wr: IN std_logic; -- write to the codec DAC
023- adc_out: OUT std_logic_vector(ADC_WIDTH-1 DOWNTO 0); -- ADC output
024- dac_in: IN std_logic_vector(DAC_WIDTH-1 DOWNTO 0); -- DAC input
025- adc_out_rdy: OUT std_logic; -- ADC output is ready to be read
026- adc_overrun: OUT std_logic; -- ADC overwritten before being read
027- dac_in_rdy: OUT std_logic; -- DAC input is ready to be written
028- dac_underrun: OUT std_logic; -- input to DAC arrived late
029- -- codec chip I/O signals
030- sdin: OUT std_logic; -- serial output to codec DAC
031- sdout: IN std_logic -- serial input from codec ADC
032- );
033- END channel;
034-
035- ARCHITECTURE channel_arch OF channel IS
036- SIGNAL dac_shfreg: std_logic_vector(DAC_WIDTH-1 DOWNTO 0);
037- SIGNAL dac_empty: std_logic; -- DAC shift register is empty
038- SIGNAL dac_wr: std_logic; -- the DAC channel has been written
039- SIGNAL dac_wr_nxt: std_logic; -- the DAC channel has been written
040- SIGNAL dac_in_rdy_int: std_logic; -- internal version of dac_in_rdy
041- SIGNAL adc_shfreg: std_logic_vector(ADC_WIDTH-1 DOWNTO 0);
042- SIGNAL adc_full: std_logic; -- ADC shift register is full
043- SIGNAL adc_rd: std_logic; -- the ADC channel has been read
044- SIGNAL adc_rd_nxt: std_logic; -- the ADC channel has been read
045- SIGNAL adc_out_rdy_int: std_logic; -- internal version adc_out_rdy
046- BEGIN
047- -- receives data from codec ADC
048- rcv_adc:
049- PROCESS(clk,chan_on,subcycle_cntr,bit_cntr,adc_shfreg,sdout)
050- BEGIN
051- IF(clk'event AND (clk=YES)) THEN
052- IF(reset='1') THEN
053- adc_shfreg <= (OTHERS=>'0');
054- adc_full <= NO;
055- ELSIF((chan_on=YES) AND (subcycle_cntr=2)) THEN
056- IF(bit_cntr<ADC_WIDTH-1) THEN
057- adc_full <= NO;
058- adc_shfreg <= adc_shfreg(ADC_WIDTH-2 DOWNTO 0) & sdout;
059- ELSIF(bit_cntr=ADC_WIDTH-1) THEN
060- adc_full <= YES;
061- adc_shfreg <= adc_shfreg(ADC_WIDTH-2 DOWNTO 0) & sdout;
062- END IF;
063- END IF;
064- END IF;
065- END PROCESS;
066- adc_out <= adc_shfreg;
067-
068- -- handle reading of ADC data from codec interface
069- adc_rd_nxt <= YES WHEN (adc_full=YES AND chan_sel=YES AND rd=YES) OR