XESS XStend XS40, Manual

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mclk: This output is the master clock for the codec chip.
lrck: This output controls the activation of the left and right channel circuitry in the codec
and the codec interface.
sclk: This output is the clock for synchronizing serial data transfers between the FPLD
and the codec.
sdout: The serial data stream from the codec ADCs are shifted in through this input.
sdin: The serial data stream for the codec DACs are shifted out through this output.
The following modules and processes are placed within the main body of the loopback
application:
u0: This is the instantiation of the codec interface module. Note that the ADC output
buses of this module are connected back to the DAC input buses on lines 43—46.
loop: This process controls the reading of each ADC and the writing of the value back to
the associated DAC. For example, if the output of the left channel ADC is ready to be
read and the left channel DAC is ready to be written, then the left channel is selected
and the read and write control lines are asserted. This reads the data from the ADC
shift register and writes it into the DAC shift register during a single clock cycle. Then
the ADC and DAC registers will no longer be ready for reading or writing so the read
and write signals will be deasserted.
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Listing 27: VHDL code for a design that uses the codec interface module to do loopback.
001- LIBRARY IEEE,codec;
002- USE IEEE.STD_LOGIC_1164.ALL;
003- USE codec.codec.ALL;
004-
005- ENTITY loopback IS
006- PORT
007- (
008- clk: IN STD_LOGIC; -- 12 MHz clock
009- rst: IN STD_LOGIC; -- active-high reset
010- mclk: OUT STD_LOGIC; -- master clock to codec
011- lrck: OUT STD_LOGIC; -- left/right clock to codec
012- sclk: OUT STD_LOGIC; -- serial data shift clock to codec
013- sdout: IN STD_LOGIC; -- serial data from codec ADCs
014- sdin: OUT STD_LOGIC; -- serial data to codec DACs
015- s: OUT STD_LOGIC_VECTOR(1 DOWNTO 0) –- LED segments
016- );
017- END loopback;
018-
019- ARCHITECTURE loopback_arch OF loopback IS
020- SIGNAL lrsel,rd,wr: STD_LOGIC;
021- SIGNAL left_channel,right_channel: STD_LOGIC_VECTOR(7 DOWNTO 0);
022- SIGNAL ldac_in_rdy,rdac_in_rdy: STD_LOGIC;
023- SIGNAL ladc_out_rdy,radc_out_rdy: STD_LOGIC;
024- BEGIN
025- u0: codec_intfc