XESS XStend XS40, Manual

Page: 48 / 63

47
124-
125- -- handle writing of DAC data from codec interface
126
- dac_wr_nxt <= YES WHEN (dac_empty=YES AND chan_sel=YES AND wr=YES) OR
127- (dac_empty=YES AND dac_wr=YES)
128- ELSE NO;
129- write_dac:
130- PROCESS(clk,reset,dac_wr_nxt)
131- BEGIN
132- IF(clk'event AND clk='1') THEN
133- IF(reset=YES) THEN
134- dac_wr <= NO;
135- ELSE
136- dac_wr <= dac_wr_nxt;
137- END IF;
138- END IF;
139- END PROCESS;
140- -- DAC is ready if register is empty and hasn't been written yet
141- dac_in_rdy_int <= YES WHEN dac_empty=YES AND dac_wr=NO ELSE NO;
142- dac_in_rdy <= dac_in_rdy_int;
143-
144- -- detect and signal underflow of data to the codec DAC channels
145- detect_dac_underrun:
146- PROCESS(clk,reset,bit_cntr,chan_on,dac_in_rdy_int)
147- BEGIN
148- IF(clk'event AND clk='1') THEN
149- IF(reset=YES) THEN
150- dac_underrun <= NO;
151- ELSIF(bit_cntr=1 AND chan_on=YES AND dac_in_rdy_int=YES) THEN
152- dac_underrun <= YES;
153- END IF;
154- END IF;
155- END PROCESS;
156- END channel_arch;
The VHDL code for the top-level module that combines the clock generator module with
two channel modules is detailed in
Listing 25 . The inputs and outputs of the top-level
module as defined in the entity declaration are as follows:
clk: This is the main clock input, which is typically the 12 MHz clock from the XS Board.
reset: This input synchronously resets the two channel modules and the clock generator.
lrsel: This input selects either the right or left channel for parallel read or write operations.
rd: A high level on this input outputs the value stored in the selected shift register
connected to the ADC.
wr: A high level on this input writes a new value into the selected shift register connected
to the DAC.
ladc_out, radc_out: The bits stored in the left and right ADC shift registers are read out in
parallel through these outputs..