XESS XStend XS40 Manual Download Page 30

Page: 30 / 63

reaches 527, it rolls over to zero on the next cycle. Thus, the counter has a period of
528 lines. Since the duration of a line of pixels is 31.75

s, this makes the frame

interval equal to 16.76 ms.

generate_horiz_sync:

This process describes the operation of the horizontal sync pulse

generator. The horizontal sync is set to its inactive high level when the reset is
activated. During normal operations, the horizontal sync output is updated on every
pixel clock. The sync signal goes low on the cycle after the pixel counter reaches 291
and continues until the cycle after the counter reaches 337. This gives a low
horizontal sync pulse of (337-291)=46 pixel clocks. With a pixel clock of 12 MHz, this
translates to a low-going horizontal sync pulse of 3.83

s. The sync pulse starts 292

clocks after the line of pixels begin, which translates to 24.33

s. This is less than the

26.11

s we stated before. The difference of 1.78 ms translates to 21 pixel clocks.

This time interval corresponds to the 23 blank pixels that are placed before the 256
viewable pixels (minus two clock cycles for pipelining delays).

generate_vert_sync:

This process describes the operation of the vertical sync pulse

generator. The vertical sync is set to its inactive high level when the reset is activated.
During normal operations, the vertical sync output is updated after every line of pixels
is completed. The sync signal goes low on the cycle after the line counter reaches
493 and continues until the cycle after the counter reaches 495. This gives a low
vertical sync pulse of (495-493)= 2 lines. With a line interval of 31.75

s, this

translates to a low-going vertical sync pulse of 63.5

s. The vertical sync pulse starts

494

31.75

s = 15.68 ms after the beginning of the first video line.

Line 91:

This line describes the computation of the combinatorial blanking signal. The

video is blanked after 256 pixels on a line are displayed, or after 480 lines are
displayed.

pipeline_blank:

This process describes the operation of the pipelined video blanking

signal. Within the process, the blanking signal is stored in a register so it can be used
during the next stage of the pipeline when the color is computed.

Lines 104 -- 106:

On these lines, the RAM is permanently selected and writing to the

RAM is disabled. This makes the RAM look like a ROM, which stores video data. In
addition, the outputs from the RAM are disabled when the video is blanked since
there is no need for pixels during the blanking intervals. This isn’t really necessary
since no other circuit is trying to access the RAM.

Line 113:

The address in RAM where the next four pixels are stored is calculated by

concatenating the lower nine bits of the line counter with bits 7,6,5,4,3 and 2 of the
pixel counter. With this arrangement, the line counter stores the address of one of 2

= 512 pages. Each page contains 2

= 64 bytes. Each byte contains four pixels, so

each page stores one line of 256 pixels. The pixel counter increments through the
bytes of a page to get the pixels for the current line. (Note that we don’t need to use
bits 1 and 0 of the pixel counter when computing the RAM address since each byte
contains four pixels.) After the line is displayed, the line counter is incremented to
point to the next page.

update_pixel_register:

This process describes the operation of the register that holds the

byte of pixel data read from RAM. The register is asynchronously cleared when the
VGA circuit is reset. The register is updated on the rising edge of each pixel clock.
The pixel register is loaded with data from the RAM whenever the lowest two bits of