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WCH CH32V003 Series, Reference Manual

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WCH CH32V003 Series Reference Manual Download Page 98

CH32V003

 

Reference Manual

 

 

http://wch.cn

 

 

V1.3

 

 

98 

   

 

the  synchronization  information  (TRGO)  sent  to  the 
slave timer in master mode. The possible combinations 
are as follows. 
000: The  UG  bit  of  the  Reset-TIMx_EGR  register  is 
used as the trigger output (TRGO). In the case of a reset 
generated by a trigger input (from a mode controller in 
reset  mode),  there  is  a  delay  in  the  signal  on  TRGO 
relative to the actual reset. 
001:  Enable  - The  counter  enable  signal  CNT_EN  is 
used  as  a  trigger  output  (TRGO).  Sometimes  it  is 
necessary to start multiple timers at the same time or to 
control  the  enable  from  timers  over  a  period  of  time. 
The counter enable signal is generated by the logical or 
of the trigger input signal in CEN control bit and gated 
mode. When the counter enable signal is controlled by 
a  trigger  input,  there  is  a  delay  on  TRGO  unless 
master/slave mode is selected (see the description of the 
MSM bit in the TIMx_SMCR register). 
010: Update - The update event is selected as a trigger 
input (TRGO). For example, the clock of a master timer 
may be used as a prescaler for a slave timer. 
011: comparison pulse - on the occurrence of a capture 
or a successful comparison, when the CC1IF flag is to 
be  set  (even  if  it  is  already  high),  the  trigger  output 
sends a positive pulse (TRGO). 
100:  The  comparison-OC1REF  signal  is  used  as

 

a 

trigger output (TRGO). 
101:  The  comparison-OC2REF  signal  is  used  as  a 
trigger output (TRGO). 
110:  The  comparison-OC3REF  signal  is  used  as  a 
trigger output (TRGO). 
111: The compare-OC4REF signal is used as the trigger 
output (TRGO). 

3 

CCDS 

RW 

Capture the DMA selection for comparison. 
1:  Sending  a  DMA  request  for  CHxCVR  when  an 
update event occurs. 
0:  Generate  a  DMA  request  for  CHxCVR  when 
CHxCVR occurs. 

0 

2 

CCUS 

RW 

Compare capture control update selection bits. 
1: if CCPC is set, they can  be updated by setting the 
COM bit or a rising edge on TRGI. 
0:  If  the  CCPC  is  set,  they  can  only  be  updated  by 
setting the COM bit. 

Note:  This  bit  only  works  for  channels  with 
complementary outputs. 

0 

1 

Reserved 

RO  Reserved 

0 

0 

CCPC 

RW 

Compare capture preload control bits. 
1: the CCxE, CCxNE and OCxM bits are preloaded and 
when  this  bit  is  set  they  are  only  updated  when  the 
COM bit is set. 
0: CCxE, CCxNE and OCxM bits are not preloaded. 

Note:  This  bit  only  works  for  channels  with 
complementary outputs. 

0 

 

10.4.3 Slave Mode Control Register (TIM1_SMCFGR) 

Offset address: 0x08 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

ETP  ECE  ETPS[1:0] 

ETF[3:0] 

MSM 

TS[2:0] 

Reserved 

SMS[2:0] 

Summary of Contents for CH32V003 Series

Page 1: ...unctional chapters RISC V core version overview Features Core versions Instruction set Hardware stack levels Interrupt nesting levels Number of fast interrupt channels Integer division periodicity Vector table model Extensions instruction Memory protection QingKe V2A RV32EC 2 2 2 None Address or command Support None Abbreviated description of the bit attribute in the register Register bit properti...

Page 2: ...X LSI RC HSE HSI RC 2 SYSCLK Reset MUX DIV IWDG_CLK OSC_IN OSC_OUT SWIO VDD 2 7V 5 5V VSS DMA 7 Channels TIM1 USART PWR VDD RX TX CTS RTS CK 4 channels 3 complementary Channels ETR BIKN SCL SDA MUX System Bus AH B F max 50MHz IWDG EXTI EXTEN ADC AHBCLK AIN0 AIN7 ETR ETR2 GPIO PWR_CLK WWDG TIM2 4 channels ETR AFIO I2C GPIOA GPIOC PA1 PA2 PC0 PC7 GPIOD PD0 PD7 SPI MOSI MISO SCK NSS Amplify Compare O...

Page 3: ...responsible for the DMAof theAHB master interface connected to the bus matrix which is accessed by FLASH data SRAM and peripherals l The BusMatrix is responsible for the access coordination between the system bus data bus DMA bus SRAM and AHB APB bridge l The AHB bridge provides full synchronous connections between the AHB bus and the two APB buses With different peripherals hooked up under differ...

Page 4: ...ddress space Peripherals 2KB SRAM 0x2000 0800 0x0000 0000 0x0800 0000 0x1FFF F000 0x4000 0000 0x4000 0400 0xE000 0000 0xFFFF FFFFF 0x4000 0000 0xE010 0000 Core Private Peripherals FLASH 0x1FFF F780 0x1FFF F800 0x1FFF FFFF Code FLASH 16KB System FLASH BOOT_1920B 0x1FFF F840 Aliased to Flash or system memory depending on software configuration 0x4000 2C00 0x4000 3000 0x4000 3400 0x4001 2800 0x4001 1...

Page 5: ...and full word 4 bytes access Built in 16KB program Flash memory CodeFlash for storing user applications Built in 1920B System memory bootloader for storing the system bootloader factory cured bootloader Built in 64B space for vendor configuration word storage factory cured and unmodifiable by users Built in 64B space for user selected word storage ...

Page 6: ...rnal power on reset POR and a power down reset PDR circuit When the chip supply voltage VDD falls below the corresponding threshold voltage the system is reset by the relevant circuit and no additional external reset circuit is required Please refer to the corresponding datasheet for the parameters of the power on threshold voltage VPOR and the power down threshold voltage VPDR Figure 2 2 Schemati...

Page 7: ...te run mode where system power can be saved by reducing the system main frequency or turning off the unused peripheral clock or reducing the operating peripheral clock If the system does not need to work you can set the system to enter low power mode and let the system jump out of this state by specific events Microcontrollers currently offer 2 low power modes divided in terms of operating differe...

Page 8: ... pins keep their state in Run mode and all peripheral clocks are normal so try to turn off useless peripheral clocks before entering Sleep mode to reduce low power consumption This mode takes the shortest time to wake up Enter Configure core register control bit SLEEPDEEP 0 power control register PDDS 0 execute WFI or WFE optionally SEVONPEND and SLEEPONEXIT Exit Arbitrary interrupt or wakeup even...

Page 9: ...on Reset value 31 8 Reserved RO Reserved 0 7 5 PLS 2 0 RW PVD voltage monitoring threshold setting See the Electrical Characteristics section of the datasheet for detailed instructions 000 2 85V rising edge 2 7V falling edge 001 3 05V rising edge 2 9V falling edge 010 3 3V rising edge 3 15V falling edge 011 3 5V rising edge 3 3V falling edge 100 3 7V rising edge 3 5V falling edge 101 3 9V rising e...

Page 10: ...d AWU EN Reser ved Bit Name Access Description Reset value 31 2 Reserved RO Reserved 0 1 AWUEN RW Enable Automatic wake up 1 Turn on auto wakeup 0 Invalid 0 0 Reserved RO Reserved 0 2 4 4 Auto wakeup window comparison value register PWR_ AWUWR Offset address 0x0C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved AWUUWR Bit Name Access Descripti...

Page 11: ... RW Counting time base 0000 Prescaler off 0001 Prescaler off 0010 Divided by 2 0011 Divided by 4 0100 Divided by 8 0101 Divided by 16 0110 Divided by 32 0111 Divided by 64 1000 Divided by 128 1001 Divided by 256 1010 Divided by 512 1011 Divided by 1024 1100 Divided by 2048 1101 Divided by 4096 1110 Divided by 0x2800 1111 Divided by 0xf000 0 ...

Page 12: ...register RCC_RSTSCKR and all the registers The source of the reset event is identified by looking at the reset status flag bit in the RCC_RSTSCKR register A system Reset is generated when one of the following events occurs l Low signal on NRST pin external reset l Window watchdog count termination WWDG reset l Independent watchdog count termination IWDG reset l Software reset SW reset l Low power ...

Page 13: ...CH32V003 Reference Manual http wch cn V1 3 12 Figure 3 1 System reset structure System Reset Power Reset Software Reset WWDG Reset IWDG Reset Low power management Reset RPU VDD VDDA NRST ...

Page 14: ...HSI PLLCLK AHB prescaler 1 2 256 to Flash register FCLK core free running clock SYSCLK 48MHz max HCLK RCC_CFGR0 PLLSRC peripheral clock enable to SRAM DMA to AHB peripherals peripheral clock enable to TIM2 to TIM1 2 4 6 8 12 1 6 64 96 128 ADCPRE to ADC to IWDG 3 to Flash time base HSI CSS 8 to Core System Timer peripheral clock enable SW peripheral clock enable peripheral clock enable to gpio inte...

Page 15: ...high speed clock signal including external crystal ceramic resonator generation or external high speed clock feed l External Crystal Ceramic Resonator HSE Crystal An external 4 25MHz oscillator provides a more accurate clock source for the system Further information can be found in the Electrical Characteristics section of the datasheet The HSE crystal can be turned on and off by setting the HSEON...

Page 16: ...k l HSE Clock 3 3 5 Bus Peripheral clock 3 3 5 1 System clock SYSCLK Configure the system clock source by configuring the RCC_CFGR0 register SW 1 0 bits SWS 1 0 indicates the current system clock source l HSI as system clock l HSE as system clock l PLL as system clock After a controller reset the default HSI clock is selected as the system clock source Switching between clock sources must occur on...

Page 17: ...ters the NMI non maskable interrupt By setting the CSSC bit the CSSF bit flag can be cleared and the NMI interrupt pending bit can be undone If the current HSE is used as the system clock or if the current HSE is used as the PLL input clock and the PLL is used as the system clock the clock safety system will automatically switch the system clock to the HSI oscillator and turn off the HSE oscillato...

Page 18: ...d Note After the HSEON bit is cleared to 0 it takes 6 HSE cycles for this bit to clear to 0 0 16 HSEON RW External high speed crystal oscillation enable control bit 1 Enables the HSE oscillator 0 Turn off the HSE oscillator Note This bit is cleared to 0 by hardware after entering Standby low power mode 0 15 8 HSICAL RO Internal high speed clock calibration values which are automatically initialize...

Page 19: ... 010xx AHBCLK divided by 4 as ADC clock 100xx AHBCLK divided by 6 as ADC clock 110xx AHBCLK divided by 8 as ADC clock 00100 AHBCLK divided by 4 as ADC clock 01100 AHBCLK divided by 8 as ADC clock 10100 AHBCLK divided by 12 as ADC clock 11100 AHBCLK divided by 16 as ADC clock 00101 AHBCLK divided by 8 as ADC clock 01101 AHBCLK divided by 16 as ADC clock 10101 AHBCLK divided by 24 as ADC clock 11101...

Page 20: ...oscillator HSE used as the system clock fails 0 3 4 3 Clock interrupt register RCC_INTR Offset address 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved CS SC Reserved PLL RDY C HSE RDY C HSI RDY C Reser ved LSI RDY C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PLL RDYI E HSE RDYI E HSI RDYI E Reserv ed LSI RDYIE CS SF Reserved PLL RDY F HSE RDY F HSI RDY F Reser ved LSI RDY F Bit N...

Page 21: ...et software write PLLRDYC bit 1 cleared 0 3 HSERDYF RO HSE clock ready interrupt flag 1 HSE clock ready interrupt generation 0 No HSE clock ready interrupt Hardware set software write HSERDYC bit 1 cleared 0 2 HSIRDYF RO HSI clock ready interrupt flag 1 HSI clock ready interrupt generation 0 No HSI clock ready interrupt Hardware set software write HSIRDYC bit 1 cleared 0 1 Reserved RO Reserved 0 0...

Page 22: ...B1PRSTR Offset address 0x10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PWR RST Reserved I2C1 RST Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WW DG RST Reserved TIM 2 RST Bit Name Access Description Reset value 31 29 Reserved RO Reserved 0 28 PWRRST RW Power interface module reset control 1 Reset module 0 No effect 0 27 22 Reserved RO Reserved 0 21 I2C1RST RW I2C 1 interfa...

Page 23: ...Reset value 31 15 Reserved RO Reserved 0 14 USART1EN RW USART1 interface clock enable bit 1 Module clock is on 0 Module clock is off 0 13 Reserved RO Reserved 0 12 SPI1EN RW SPI1 interface clock enable bit 1 Module clock is on 0 Module clock is off 0 11 TIM1EN RW TIM1 module clock enable bit 1 Module clock is on 0 Module clock is off 0 10 Reserved RO Reserved 0 9 ADC1EN RW ADC1 module clock enable...

Page 24: ...heral clock is not enabled the software cannot read out the peripheral register value and the value returned is always 0 3 4 9 Control Status register RCC_RSTSCKR Offset address 0x24 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LPW R RSTF WW DG RSTF IWD G RSTF SFT RSTF POR RSTF PIN RSTF Reser ved RMV F Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LSI RDY LSION Bit Name Access Descrip...

Page 25: ...ST pin reset 0 No NRST pin reset occurs Set to 1 by hardware when NRST pin reset occurs cleared by software writing of RMVF bit 0 25 Reserved RO Reserved 0 24 RMVF RW Clear reset flag control 1 Clear the reset flag 0 No effect 0 23 2 Reserved RO Reserved 0 1 LSIRDY RO Internal Low Speed Clock LSI Stable Ready flag bit set by hardware 1 Stable internal low speed clock 128KHz 0 The internal low spee...

Page 26: ...er turns the watchdog on after which it cannot be turned off again unless a reset occurs If the hardware independent watchdog enable bit IWDG_SW is turned on at the user selected word IWDG will be fixed on after a microcontroller reset l Watchdog configuration The watchdog is internally a 12 bit counter that runs decreasingly When the counter value decreases to 0 a system Reset will occur To turn ...

Page 27: ...set address 0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY 15 0 Bit Name Access Description Reset value 15 0 KEY WO Operate the key value lock 00xAAAA Feed the dog Loading of the IWDG_RLDR register value into the independent watchdog counter 0x5555 Allows modification of the R16_IWDG_PSCR and R16_IWDG_ RLDR registers 0xCCCC Start the watchdog but not if the hardware watchdog is enabled user select...

Page 28: ... address 0x0C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RVU PVU Bit Name Access Description Reset value 15 2 Reserved RO Reserved 0 1 RVU RO Reload value update flag bit Hardware set or clear 0 1 Reload value update is in progress 0 End of reload update up to 5 LSI cycles Note The reload value register IWDG_RLDR can only be accessed read or write after the RVU bit is cleared to 0 0 0 PVU RO C...

Page 29: ...hether the watchdog function is on or not As shown in Figure 5 1 the block diagram of the internal structure of the window watchdog Figure 5 1 Block diagram of Window Watchdog structure W6 W5 W4 W3 W2 W1 W0 WDGA T6 T5 T4 T3 T2 T1 T0 4096 WDGTB 1 0 PCLK1 Watchdog control register WWDG_CTLR RESET WriteWWDG_CTLR 6 0 Watchdog configurationregister WWDG_CFGR T 6 0 W 6 0 WWDG_CLK WWDG enablecontrol soft...

Page 30: ...to 0x3F due to no timely dog feeding operation a window watchdog reset will occur and a system reset will be generated That is the T6 bit is detected as 0 by the hardware and a system reset will occur Note The application can write T6 bit to 0 by software to achieve system Reset which is equivalent to software reset function 2 When the counter refresh action is executed within the disallowed dog f...

Page 31: ...1 is on but only allows hardware to clear 0 after reset 0 6 0 T RW The 7 bit self decrement counter decrements by 1 every 4096 2WDGTB PCLK1 cycles A watchdog reset is generated when the counter decrements from 0x40 to 0x3F i e when T6 jumps to 0 7Fh 5 3 2 Configuration register WWDG_CFGR Offset address 0x04 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EWI WDGTB 1 0 W 6 0 Bit Name Access Descript...

Page 32: ...t address 0x08 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EWIF Bit Name Access Description Reset value 15 1 Reserved WO Reserved 0 0 EWIF RW0 Wake up the interrupt flag bit early When the counter reaches 0x40 this bit is set in hardware and must be cleared to 0 by software the user setting is invalid Even if the EWI is not set this bit will still be set as usual when the event occurs 0 ...

Page 33: ...able 6 1 CH32V003 series vector table No Priority Type Name Description Entrance address 0 0x00000000 1 0x00000004 2 2 fixed NMI Non maskable interrupts 0x00000008 3 1 fixed HardFault Abnormal interruptions 0x0000000C 4 11 Reserved 0x00000010 0x0000002C 12 0 programmable SysTick System timer interrupt 0x00000030 13 Reserved 0x00000034 14 1 programmable SW Software interrupt 0x00000038 15 Reserved ...

Page 34: ...oller 10 10 10 10 10 10 10 10 Input Line As can be seen from Figure 6 1 the trigger source of the external interrupt can be either a software interrupt SWIEVR or an actual external interrupt channel The signal of the external interrupt channel will be screened by the edge detect circuit first Whenever one of the software interrupt or external interrupt signals is generated it will be output to two...

Page 35: ...t EXTI_EVENR for the corresponding external interrupt channel 3 Configure the trigger edge EXTI_RTENR or EXTI_FTENR to select rising edge trigger falling edge trigger or double edge trigger Using the software interrupt event steps 1 Enabling external interrupts EXTI_INTENR or external events EXTI_EVENR 2 If using interrupt service functions the EXTI interrupt needs to be set in the core s PFIC 3 S...

Page 36: ...5 MR4 MR3 MR2 MR1 MR0 Bit Name Access Description Reset value 31 10 Reserved RO Reserved 0 9 0 MRx RW Enable the event request signal for external interrupt channel x 1 Event enabling this channel 0 Block the events of this channel 0 6 5 1 3 Rising edge trigger enable register EXTI_RTENR Offset address 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 37: ...I_INTENR or event enable EXTI_EVENR is on then an interrupt or event will be generated 0 6 5 1 6 Interrupt flag register EXTI_INTFR Offset address 0x14 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IF9 IF8 IF7 IF6 IF5 IF4 IF3 IF2 IF1 IF0 Bit Name Access Description Reset value 31 10 Reserved RO Reserved 0 9 0 IFx W1 The interrupt flag bit t...

Page 38: ...TR2 0xE000E304 PFIC interrupt activation status register 2 0x00000000 R32_PFIC_IPRIORx 0xE000E400 PFIC interrupt priority configuration register 0x00000000 R32_PFIC_SCTLR 0xE000ED10 PFIC system control register 0x00000000 Note 1 The default value of PFIC_ISR0 register is 0xC that is NMI and exception are always enabled by default 2 NMI and EXC support interrupt pending clear and setting operation ...

Page 39: ...t address 0x20 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PENDSTA 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reser ved PEN DST A14 Reser ved PEN DST A12 Reserved PEN DST A3 PEN DST A2 Reserved Bit Name Access Description Reset value 31 16 PENDSTA16_31 RO 1216 31 interrupt the current pending status 1 The current number break is pending 0 The current number break is not pending 0 15 Reserved ...

Page 40: ...ved RO Reserved 0 7 0 THRESHOLD RW Interrupt priority threshold setting value The interrupt priority value lower than the current setting value when hung does not perform interrupt service this register is 0 means the threshold register function is invalid 7 6 priority threshold 5 0 reserved fixed to 0 write invalid 0 6 5 2 6 PFIC interrupt configuration register PFIC_CFGR Offset address 0x48 31 3...

Page 41: ...ent interrupt nesting status currently supports a maximum of 2 levels of nesting and a maximum hardware stack depth of 2 levels 0x03 Level 2 interrupt in progress 0x01 Level 1 interrupt in progress Other no interrupt occurred 0 6 5 2 8 PFIC VTF interrupt ID configuration register PFIC_VTFIDR Offset address 0x50 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 42: ...interrupt 1 channel is enabled 0 Off 0 6 5 2 11 PFIC interrupt enable setting register 1 PFIC_IENR1 Offset address 0x100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INTEN 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reser ved INTEN1 4 Rese rved INTEN12 Reserved Bit Name Access Description Reset value 31 16 INTEN16_31 WO 16 31 interrupt enable control 1 current number interrupt enable 0 No effec...

Page 43: ...rrupt off 0 No effect 0 15 Reserved RO Reserved 0 14 INTRSET14 WO 14 Interrupt off control 1 current number interrupt off 0 No effect 0 13 Reserved RO Reserved 0 12 INTRSET12 WO 12 Interrupt off control 1 current number interrupt off 0 No effect 0 11 0 Reserved RO Reserved 0 6 5 2 14 PFIC interrupt enable clear register 2 PFIC_IRER2 Offset address 0x184 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 44: ... 0 Reserved RO Reserved 0 6 5 2 16 PFIC interrupt pending setup register 2 PFIC_IPSR2 Offset address 0x204 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PENDSET 38 32 Bit Name Access Description Reset value 31 7 Reserved RO Reserved 0 6 0 PENDSET32_38 WO 32 38 interrupt pending setting 1 current number break hang 0 No effect 0 6 5 2 17 PFIC...

Page 45: ...31 7 Reserved RO Reserved 0 6 0 PENDRESET32_38 WO 32 38 interrupt hang clear 1 The current numbered interrupt clears the pending state 0 No effect 0 6 5 2 19 PFIC interrupt activation status register 1 PFIC_IACTR1 Offset address 0x300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IACTS 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reser ved IACTS1 4 Reser ved IACTS1 2 Reserved IACTS 3 IACTS 2 Rese...

Page 46: ...nfiguration Register PFIC_IPRIORx x 0 63 Offset address 0x400 0x4FF The controller supports 256 interrupts 0 255 each using 8 bits to set the control priority 31 24 23 16 15 8 7 0 IPRIOR63 PRIO_255 PRIO_254 PRIO_253 PRIO_252 IPRIORx PRIO_ 4x 3 PRIO_ 4x 2 PRIO_ 4x 1 PRIO_ 4x IPRIOR0 PRIO_3 PRIO_2 PRIO_1 PRIO_0 Bit Name Access Description Reset value 2047 2040 IP_255 RW Same as IP_0 description 0 31...

Page 47: ...a WFE 1 treat the subsequent WFI instruction as a WFE instruction 0 No effect 0 2 SLEEPDEEP RW Low power mode of the control system 1 deep sleep 0 sleep 0 1 SLEEPONEXIT RW System status after control leaves the interrupt service program 1 The system enters low power mode 0 The system enters the main program 0 0 Reserved RO Reserved 0 6 5 3 Dedicated CSR registers A number of Control and Status Reg...

Page 48: ...le identifies patterns 0 identification by jump instruction limited range support for non jump instructions 1 Identify by absolute address support full range but must jump 0 0 MODE0 MRW Interrupt or exception entry address mode selection 0 use of a unified entry address 1 Address offset based on interrupt number 4 0 6 5 4 STK register description Table 6 5 STK related registers list Name Access ad...

Page 49: ...ontrol bit 1 Enabling counter interrupts 0 Turn off the counter interrupt 0 STE RW System counter enable control bit 1 Start the system counter STK 0 Turn off the system counter STK and the counter stops counting 0 6 5 4 2 System count status register STK_SR Offset address 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CNTI F Bit Name A...

Page 50: ...nting comparison register STK_CMPLR Offset address 0x10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CMP 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMP 15 0 Bit Name Access Description Reset value 31 0 CMP RW Set the comparison counter value to 32 bits 0 ...

Page 51: ...re block diagram As shown in Figure 7 1 I O port structure each pin has two protection diodes inside the chip and the I O port can be divided into input and output driver modules internally Among them the input driver has a weak pull up and pull down resistor optional which can be connected to AD and other analog input peripherals if the input is to a digital peripheral it needs to go through a TT...

Page 52: ...ed output mode push pull or open drain can be set according to the actual situation l For bidirectional multiplexing the port must be configured in multiplexed output mode when the driver is configured in floating input mode The same I O port may have multiple peripherals multiplexed to this pin so in order to maximize the space for each peripheral the multiplexed pins of peripherals can be remapp...

Page 53: ... configured to open drain or push pull mode as desired the Schmitt trigger is turned on the input and output lines of the multiplexing function are connected but the output data registers are disconnected and the levels appearing on the I O pins will be sampled into the input data registers at each APB2 clock In open drain mode reading the input data register will give the current status of the I ...

Page 54: ...l purpose timer TIM2 TIM2 pins Configuration GPIO configuration TIM2_CHx Input capture channel x Floating input Output comparison channel x Push pull multiplexed output TIM2_ETR Externally triggered clock input Floating input Table 7 3 Universal synchronous asynchronous serial transceiver USART USART pins Configuration GPIO configuration USARTx_TX Full duplex mode Push pull multiplexed outputs Hal...

Page 55: ...External interrupt input Float pull up or pull down input OPA Operational Amplifier Input Floating input 7 3 Register description 7 3 1 GPIO register description Unless otherwise specified the registers of the GPIO must be operated as words operate these registers with 32 bits Table 7 8 GPIO related registers list Name Access address Description Reset value R32_GPIOA_CFGLR 0x40010800 PA port confi...

Page 56: ...igured When in input mode MODE 00b 00 Analog input mode 01 Floating input mode 10 With pull up and pull down mode 11 Reserved In output mode MODE 00b 00 Universal push pull output mode 01 Universal open drain output mode 10 Multiplexed function push pull output mode 11 Multiplexing function open drain output mode 01b 29 28 25 24 21 20 17 16 13 12 9 8 5 4 1 0 MODEy RW y 0 7 port x mode selection co...

Page 57: ... BS5 BS4 BS3 BS2 BS1 BS0 Bit Name Access Description Reset value 31 24 Reserved R0 Reserved 0 23 16 BRy WO y 0 7 the corresponding OUTDR bits are cleared for these location bits and writing 0 has no effect These bits can only be accessed in 16 bit form If both BR and BS bits are set the BS bit takes effect 0 15 8 Reserved RO Reserved 0 7 0 BSy WO y 0 7 for which the location bits will make the cor...

Page 58: ...he lock is in effect the port configuration can only be changed after the next reset 0 7 0 LCKy RW y 0 7 these bits are 1 to indicate locking the configuration of the corresponding port These bits can only be changed before the LCKK is unlocked The locked configuration refers to the configuration registers GPIOx_CFGLR and GPIOx_CFGHR 0 Note After the LOCK sequence is executed for the corresponding...

Page 59: ...TX PD5 RX PD6 CTS PD3 RTS PC2 SW_RX PD5 01 Remapping CK PD7 TX PD0 RX PD1 CTS PC3 RTS PC2 SW_RX PD0 10 Remapping CK PD7 TX PD6 RX PD5 CTS PC6 RTS PC7 SW_RX PD6 11 Remapping CK PC5 TX PC0 RX PC1 CTS PC6 RTS PC7 SW_RX PC0 0 20 19 Reserved RO Reserved 0 18 ADC_ETRGREG_R M RW Remap bit for ADC external trigger rule conversion 0 ADC external trigger rule conversion connected to PD3 1 ADC external trigg...

Page 60: ...H3N PC6 0 5 3 Reserved RO Reserved 0 2 USART1_RM RW USART1 mapping configuration low bit used in conjunction with AFIO PCFR1 register bit21 USART1REMAP1 21 2 00 Default mapping CK PD4 TX PD5 RX PD6 CTS PD3 RTS PC2 SW_RX PD5 01 Remapping CK PD7 TX PD0 RX PD1 CTS PC3 RTS PC2 SW_RX PD0 10 Remapping CK PD7 TX PD6 RX PD5 CTS PC6 RTS PC7 SW_RX PD6 11 Remapping CK PC5 TX PC0 RX PC1 CTS PC6 RTS PC7 SW_RX ...

Page 61: ... 0 Bit Name Access Description Reset value 31 16 Reserved RO Reserved 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTIx RW x 0 7 external interrupt input pin configuration bit Used to determine to which port pins the external interrupt pins are mapped 00 xth pin of the PA pin 10 xth pin of the PC pin 11 xth pin of the PD pin 0 ...

Page 62: ...heral memory access to be initiated based on the priority of the channel request In software management the application can configure the priority level for each channel independently by setting the PL 1 0 bits of the DMA_CFGRx register including four levels highest high medium and low When the software setting levels are the same between channels the module will be selected according to a fixed h...

Page 63: ...operation will continue until the channel is turned off or the DMA mode is turned off 4 DMA processing status l Transfer half It corresponds to the hardware setting of HTIFx bit in DMA_INTFR register The DMA transfer half flag will be generated when the number of DMA transfers is reduced to less than half of the initial set value and an interrupt will be generated if HTIE is set in the DMA_CCRx re...

Page 64: ...get data bit width l DMA transfer of data sent to the target based on the principle the high bit of the data size is not enough to make up 0 the high bit of the data size overflow is removed l Storage data mode small end mode low address stores low bytes high address stores high bytes 8 16 4 0x00 B0 0x01 B1 0x02 B2 0x03 B3 0x00 00B0 0x02 00B1 0x04 00B2 0x06 00B3 8 32 4 0x00 B0 0x01 B1 0x02 B2 0x03...

Page 65: ...3 Register description Table 8 3 DMA related registers list Name Access address Description Reset value R32_DMA_INTFR 0x40020000 DMA interrupt status register 0x00000000 R32_DMA_INTFCR 0x40020004 DMA interrupt flag clear register 0x00000000 R32_DMA_CFGR1 0x40020008 DMA channel 1 configuration register 0x00000000 R32_DMA_CNTR1 0x4002000C DMA channel 1 number of data register 0x00000000 R32_DMA_PADD...

Page 66: ...hannel 7 configuration register 0x00000000 R32_DMA_CNTR7 0x40020084 DMA channel 7 number of data register 0x00000000 R32_DMA_PADDR7 0x40020088 DMA channel 7 peripheral address register 0x00000000 R32_DMA_MADDR7 0x4002008C DMA channel 7 memory address register 0x00000000 8 3 1 DMA Interrupt status register DMA_INTFR Offset address 0x00 x 1 0x400 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reser...

Page 67: ...tion flag for channel x x 1 2 3 4 5 6 7 1 Clear the TCIFx flag in the DMA_INTFR register 0 No effect 0 24 20 16 1 2 8 4 0 CGIFx WO Clear the global interrupt flag for channel x x 1 2 3 4 5 6 7 1 Clear the TEIFx HTIFx TCIFx GIFx flags in the DMA_INTFR register 0 No effect 0 8 3 3 DMA Channel x configuration register DMA_CFGRx x 1 2 3 4 5 6 7 Offset address 0x08 x 1 20 y 1 0x400 31 30 29 28 27 26 25...

Page 68: ...transmission completion interrupt 0 0 EN RW Channel enable control 1 Channel on 0 Channel off When a DMA transfer error occurs the hardware automatically clears this bit to 0 and shuts down the channel 0 8 3 4 DMA Channel x number of data register DMA_CNTRx x 1 2 3 4 5 6 7 Offset address 0x0C x 1 20 y 1 0x400 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 ...

Page 69: ...eration address is automatically 4 byte aligned 0 Note This register can only be changed when EN 0 and cannot be written when EN 1 8 3 6 DMA Channel x memory address register DMA_MADDRx x 1 2 3 4 5 6 7 Offset address 0x14 x 1 20 y 1 0x400 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MA 31 0 Bit Name Access Description Reset value 31 0 MA RW The memory data ...

Page 70: ...e accomplished The channel voltage can be monitored to see if it is within the threshold range by using the analog watchdog function 9 1 Main features l 10 bit resolution l Supports 8 external channels and 2 internal signal sources for sampling l Multiple sampling conversion methods for multiple channels single continuous scan trigger intermittent etc l Data alignment modes left aligned right alig...

Page 71: ...onversion PD3 PC2 PD1 PA2 9 2 2 ADC configuration 1 Module power up An ADON bit of 1 in the ADC_CTLR2 register indicates that the ADC module is powered up When the ADC module enters the power up state ADON 1 from the power down mode ADON 0 a delay period tSTAB is required for the module stabilization time After that the ADON bit is written to 1 again and is used as the start signal for software to...

Page 72: ... Set the CAL bit to start the calibration function Once the calibration is finished the hardware will automatically clear the CAL bit and store the calibration code into ADC_RDATAR After that the normal conversion function can be started It is recommended to perform an ADC calibration when the ADC module is powered up Note Before starting the calibration you must ensure that the ADC module is in t...

Page 73: ...rces for rule group channels EXTSEL 2 0 Trigger source Type 000 TRGO event of timer 1 Internal signal from on chip timer 001 CH1 event of timer 1 010 CH2 event of timer 1 011 TRGO event of timer 2 100 CH1 event of timer 2 101 CH2 event of timer 2 110 PD3 PC2 events From external pins 111 SWSTART software trigger Software control bits Table 9 2 External trigger sources for injection group channels ...

Page 74: ...el scan mode repeat a new round of transitions at the end of each round until CONT clears 0 to terminate 1 0 0 1 Note The external trigger events for rule groups and injection groups are different and the ACON bit can only initiate rule group channel conversion so the initiation events for rule group and injection group channel conversion are independent 1 Single single channel conversion mode In ...

Page 75: ... prescaler factor is 2 there is a delay of 2 ADCCLK intervals 3 Single intermittent mode conversion The intermittent mode of the rule group or injection group is entered by setting the RDISCEN or IDISCEN bit of the ADC_CTLR1 register to 1 This mode differs from scanning a complete set of channels in scan mode but divides a set of channels into multiple short sequences and each external trigger eve...

Page 76: ... below the low threshold or above the high threshold The threshold settings are located in the lowest 10 valid bits of the ADC_WDHTR and ADC_WDLTR registers The AWDIE bit of the ADC_CTLR1 register is set to allow the corresponding interrupt to be generated Figure 9 4 Analog watchdog threshold area Configure the AWDSGL RAWDEN IAWDEN and AWDCH 4 0 bits of the ADC_CTLR1 register to select the channel...

Page 77: ...ster 0x00000000 R32_ADC_IDATAR1 0x4001243C ADC injected data register 1 0x00000000 R32_ADC_IDATAR2 0x40012440 ADC injected data register 2 0x00000000 R32_ADC_IDATAR3 0x40012444 ADC injected data register 3 0x00000000 R32_ADC_IDATAR4 0x40012448 ADC injected data register 4 0x00000000 R32_ADC_RDATAR 0x4001244C ADC regular data register 0x00000000 R32_ADC_DLYR 0x40012450 ADC delayed data register 0x0...

Page 78: ... 3 4 AVDD Other Invalid 01 24 Reserved RO Reserved 0 23 AWDEN RW Simulate the watchdog function enable bit on the rule channel 1 Enabling the analog watchdog on the rule channel 0 Disable the analog watchdog on the rule channel 0 22 JAWDEN RW Simulate the watchdog function enable bit on the injection channel 1 Enabling the analog watchdog on the injection channel 0 Disable the analog watchdog on t...

Page 79: ...it occurs 0 5 EOCIE RW End of conversion rule or injection channel group interrupt enable bit 1 Enables the end of conversion interrupt EOC flag 0 Turn off the end of conversion interrupt 0 4 0 AWDCH RW Analog watchdog channel selection bits 00000 analog input channel 0 00001 Analog input channel 1 01111 Analog input channel 15 0 9 3 3 ADC Control register 2 ADC_CTLR2 Offset address 0x08 31 30 29 ...

Page 80: ... 2 100 101 110 PD1 PA2 111 JSWSTART software trigger 0 11 ALIGN RW Data alignment 1 left aligned 0 right aligned 0 10 9 Reserved RO Reserved 0 8 DMA RW Direct Memory Access DMA mode enable 1 Enables DMA mode 0 Turn off DMA mode 0 7 4 Reserved RO Reserved 0 3 RSTCAL RW Reset calibration this bit is set by software and cleared by hardware after the reset is completed 1 Initialization of the calibrat...

Page 81: ...l and the channel configuration value must remain constant during the sample cycle 0 9 3 5 ADC Sample time configuration register 2 ADC_SAMPTR2 Offset address 0x10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SMP9 2 0 SMP8 2 0 SMP7 2 0 SMP6 2 0 SMP5 2 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMP5 0 SMP4 2 0 SMP3 2 0 SMP2 2 0 SMP1 2 0 SMP0 2 0 Bit Name Access Description Reset value 31 3...

Page 82: ...HT RW Analog watchdog high threshold setting value 0 Note You can change the values of WDHTR and WDLTR during the conversion process but they will take effect at the next conversion 9 3 8 ADC Watchdog low threshold register ADC_WDHTR Offset address 0x28 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LT 9 0 Bit Name Access Description Reset v...

Page 83: ...cess Description Reset value 31 30 Reserved RO Reserved 0 29 25 SQ12 RW The number of the 12th conversion channel in the rule sequence 0 9 0 24 20 SQ11 RW The number of the 11th conversion channel in the rule sequence 0 9 0 19 15 SQ10 RW The number of the 10th conversion channel in the rule sequence 0 9 0 14 10 SQ9 RW The number of the 9th conversion channel in the rule sequence 0 9 0 9 5 SQ8 RW T...

Page 84: ...rsions 0 19 15 JSQ4 RW The number of the 4th conversion channel in the injection sequence 0 9 0 14 10 JSQ3 RW The number of the 3th conversion channel in the injection sequence 0 9 0 9 5 JSQ2 RW The number of the 2th conversion channel in the injection sequence 0 9 0 4 0 JSQ1 RW The number of the 1th conversion channel in the injection sequence 0 9 0 Note Unlike the regular conversion sequence if ...

Page 85: ...er ADC_DLYR Offset address 0x50 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DLYS RC DLYVLU Bit Name Access Description Reset value 31 10 Reserved RO Reserved 0 9 DLYSRC RW External trigger source delay selection 0 Rule channel external trigger delay 1 Injection channel external trigger delay 0 8 0 DLYVLU RW External trigger delay data del...

Page 86: ...ucture of the advanced control timer can be roughly divided into three parts namely the input clock part the core counter part and the compare capture channel part The advanced control timer can be clocked from the APB bus clock CK_INT from an external clock input pin TIMx_ETR from other timers with clock output ITRx or from the input of the compare capture channel TIMx_CHx These input clock signa...

Page 87: ...C1N OC2 OC2N OC3 OC3N OC4 CK_PSC PSC prescaler CK_CNT CNT counter Repetition counter DTG 7 0 registers CC4I CC3I CC2I CC1I OC1REF OC2REF OC3REF OC4REF Capture Compare 1Register Capture Compare 2Register Capture Compare 3Register Capture Compare 4Register Prescaler Prescaler Prescaler Prescaler CC4I IC1PS CC3I CC2I CC1I IC1PS IC2PS IC3PS IC4PS U U U U BI IC1 IC2 IC3 IC4 TRC TRC TRC TRC TI1FP1 TI1FP...

Page 88: ...ected as the clock At this point CK_INT is CK_PSC 10 2 2 2 External clock source mode1 When the SMS domain is set to 111b external clock source mode 1 is enabled When external clock source 1 is enabled TRGI is selected as the source of CK_PSC it is worth noting that the source of TRGI also needs to be selected by configuring the TS domain the TS domain can select the following types of pulses as c...

Page 89: ... is equal to the value of R16_TIMx_PSC 1 CK_PSC goes through the PSC and becomes CK_INT changing the value of R16_TIM1_PSC does not take effect in real time but is updated to the PSC after an update event the update event includes a UG bit clear and reset The core of the timer is a 16 bit counter CNT CK_CNT is eventually fed to the CNT which supports incremental count mode decremental count mode a...

Page 90: ...copied to the shadow register and then the contents of the shadow register are compared to the core counter CNT 0 1 01 10 11 TI1F Edge detector ICF 3 0 TIMx_CHCTLR1 TI1F_Rising TI1F_Falling Totheslavemodecontroller TI1F_ED TI1FP1 CC1P CC1NP TIMx_CCER TI2F_Rising TI2F_Falling 0 1 from channel 2 from channel 2 TI2FP1 TRC from slave mode controller Divider 1 2 4 8 IC1 CC1S 1 0 ICPS 1 0 CC1E TIMx_CHCT...

Page 91: ...3 Configure the CCxP bit to set the polarity of the TIxFPx For example keeping the CC1P bit low and selecting rising edge jumps 4 Configure the ICxPS domain to set the ICx signal to be the crossover factor between ICxPS For example keeping ICxPS at 00b without crossover 5 Configure the CCxE bit to allow capturing the value of the core counter CNT into the compare capture register Set the CC1E bit ...

Page 92: ...capture register 2 is its duty cycle 10 3 5 PWM output mode PWM output mode is one of the basic functions of the timer PWM output mode is most commonly used to determine the PWM frequency using the reload value and the duty cycle using the capture comparison register Set 110b or 111b in the OCxM field to use PWM mode 1 or mode 2 set the OCxPE bit to enable the preload register and finally set the ...

Page 93: ...ure event which is generated by the CSS Clock Safety System After system reset the brake function is disabled by default MOE bit is low and setting the BKE bit enables the brake function The polarity of the input brake signal can be set by setting BKP and the BKE and BKP signals can be written at the same time and there is a delay of one APB clock before the actual writing so you need to wait for ...

Page 94: ...o 001b count only on TI2 edge 010b count only on TI1 edge or 011b count on both TI1 and TI2 edges connect the encoder to the input of comparison capture channels 1 and 2 and set a value for the reload value register which can be set to a larger value When in encoder mode the internal compare capture register prescaler repeat count register etc of the timer are working normally The following table ...

Page 95: ...012C14 Event generation register 0x0000 R16_TIM1_CHCTLR1 0x40012C18 Compare capture control register 1 0x0000 R16_TIM1_CHCTLR2 0x40012C1C Compare capture control register 2 0x0000 R16_TIM1_CCER 0x40012C20 Compare capture enable register 0x0000 R16_TIM1_CNT 0x40012C24 Counters 0x0000 R16_TIM1_PSC 0x40012C28 Counting clock prescaler 0x0000 R16_TIM1_ATRLR 0x40012C2C Auto reload value register 0x0000 ...

Page 96: ... in the CHCTLRx register is set only when the counter counts down 10 Central alignment mode 2 The counter counts up and down alternately The output compare interrupt flag bit of the channel configured as output CCxS 00 in the CHCTLRx register is set only when the counter counts up 11 Central alignment mode 3 The counter counts up and down alternately The output compare interrupt flag bit of the ch...

Page 97: ...n automatically set the CEN bit in hardware 0 10 4 2 Control Register 2 TIM1_CTLR2 Offset address 0x04 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 TI1S MMS 2 0 CCDS CCUS Reserved CCPC Bit Name Access Description Reset value 15 Reserved RO Reserved 0 14 OIS4 RW Output idle state 4 1 When MOE 0 if OC4N is implemented OC1 1 after deadband 0 When MOE 0 if OC4N ...

Page 98: ...pture or a successful comparison when the CC1IF flag is to be set even if it is already high the trigger output sends a positive pulse TRGO 100 The comparison OC1REF signal is used as a trigger output TRGO 101 The comparison OC2REF signal is used as a trigger output TRGO 110 The comparison OC3REF signal is used as a trigger output TRGO 111 The compare OC4REF signal is used as the trigger output TR...

Page 99: ...ng frequency to record up to N events and then produces a jump in the output 0001 sampling frequency Fsampling Fck_int N 2 0010 sampling frequency Fsampling Fck_int N 4 0011 Sampling frequency Fsampling Fck_int N 8 0100 sampling frequency Fsampling Fdts 2 N 6 0101 sampling frequency Fsampling Fdts 2 N 8 0110 sampling frequency Fsampling Fdts 4 N 6 0111 sampling frequency Fsampling Fdts 4 N 8 1000 ...

Page 100: ...t the trigger input becomes low the counter is stopped and the counter starts and stops are controlled 110 trigger mode where the counter is started on the rising edge of the trigger input TRGI and only the start of the counter is controlled 111 External clock mode 1 rising edge of the selected trigger input TRGI drives the counter 0 10 4 4 DMA interrupt enable register TIM1_DMAINTENR Offset addre...

Page 101: ...channel 3 interrupt enable bit 1 Allows comparison of capture channel 3 interrupts 0 Disable compare capture channel 3 interrupt 0 2 CC2IE RW Compare capture channel 2 interrupt enable bit 1 allows comparison of capture channel 2 interrupts 0 Disable compare capture channel 2 interrupt 0 1 CC1IE RW Compare capture channel 1 interrupt enable bit 1 allows comparison of capture channel 1 interrupts 0...

Page 102: ...bits 0 2 CC2IF RW0 Compare capture channel 2 interrupt flag bits 0 1 CC1IF RW0 Compare capture channel 1 interrupt flag bits If the compare capture channel is configured in output mode This bit is set by hardware when the counter value matches the comparison value except in centrosymmetric mode This bit is cleared by software 1 The value of the core counter matches the value of compare capture reg...

Page 103: ...nt generation bit 4 generates compare capture event 4 0 3 CC3G WO Compare capture event generation bit 3 generates compare capture event 3 0 2 CC2G WO Compare capture event generation bit 2 generates compare capture event 2 0 1 CC1G WO Compare capture event generation bit 1 generates compare capture event 1 This bit is set by software and cleared by hardware It is used to generate a compare captur...

Page 104: ...its 000 Freeze Comparison of the value of the capture register with the value of the comparison between the core counters does not work for OC1REF 001 force to set to valid level Forcing OC1REF high when the core counter has the same value as the comparison capture register 1 010 Force to set to invalid level Forcing OC1REF low when the value of the core counter is the same as the comparison captu...

Page 105: ... of the compare capture channel 2 is reduced to 3 clock cycles 0 Based on the value of the counter and compare capture register 2 compare capture channel 2 operates normally even if the flip flop is open The minimum delay to activate the compare capture channel 2 output is 5 clock cycles when the input of the flipflop has a valid edge OC2FE only works when the channel is configured to PWM1 or PWM2...

Page 106: ...01 capture triggered every 2 events 10 capture triggered every 4 events 11 Capture is triggered every 8 events 0 9 8 CC2S RW Compare the capture channel 2 input selection field these 2 bits define the direction of the channel input output and the selection of the input pin 00 comparative capture channel 1 channel is configured as an output 01 comparison capture channel 1 channel is configured as a...

Page 107: ...are the capture channel 4 prescaler configuration field 0 9 8 CC4S RW Compare capture channel 4 input selection fields 0 7 4 IC3F RW Input capture filter 3 configuration field 0 3 2 IC3PSC RW Compare capture channel 3 prescaler configuration fields 0 1 0 CC3S RW Compare capture channel 3 input selection fields 0 10 4 9 Compare Capture enable register 2 TIM1_CCER Offset address 0x20 15 14 13 12 11 ...

Page 108: ... TIM1_PSC Offset address 0x28 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 Bit Name Access Description Reset value 15 0 PSC RW The dividing factor of the prescaler of the timer the clock frequency of the counter is equal to the input frequency of the divider PSC 1 0 10 4 12 Auto reload value register TIM1_ATRLR Offset address 0x2C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATRLR 15 0 Bit Name Access ...

Page 109: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH3CVR 15 0 Bit Name Access Description Reset value 15 0 CH3CVR RW Compare the value of capture register channel 3 0 10 4 17 Compare Capture register 4 TIM1_CH4CVR Offset address 0x40 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH4CVR 15 0 Bit Name Access Description Reset value 15 0 CH4CVR RW Compare the value of capture register channel 4 0 10 4 18 Brake and Deadband...

Page 110: ...erating once CCxE 1 or CCxNE 1 OC OCN first outputs its idle level then OCx OCxN enable output signal 1 0 When the timer is not operating OC OCN output is disabled Note When LOCK level 1 is set this bit cannot be modified 0 9 8 LOCK RW Lock the function setting field 00 Disable the locking function 01 lock level 1 no DTG BKE BKP AOE OISx and OISxN bits can be written 10 Lock level 2 where the bits...

Page 111: ...ich is the value of this field 1 0 7 5 Reserved RO Reserved 0 4 0 DBA RW These bits define the offset of the DMA in continuous mode from the address where control register 1 is located 0 10 4 20 DMA Control register TIM1_DMACFGR Offset address 0x4C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAADR 15 0 Bit Name Access Description Reset value 15 0 DMAADR RW The address of the DMA in continuous mode 0 ...

Page 112: ...gnal control timer l Support DMA in multiple modes l Support incremental coding cascading and synchronization between timers 11 2 Principle and structure Figure 11 1 Block diagram of the structure of the general purpose timer 11 2 1 Overview As shown in Figure 11 1 the structure of the general purpose timer can be roughly divided into three parts namely the input clock part the core counter part a...

Page 113: ...r for counting the count cycles of the core counter 2 The comparison capture channel of the general purpose timer lacks deadband generation and has no complementary output 3 The generic timer does not have a brake signal mechanism 4 The default clocks CK_INT for general purpose timers are all from APB1 while the CK_INT for advanced control timers are all from APB2 11 2 3 Clock input This section d...

Page 114: ...ng the external clock source mode 2 ETRF is selected as CK_PSC the ETR pin becomes ETRP after passing through the optional inverter ETP divider ETPS and then ETRF after passing through the filter ETF With the ECE position bit and the SMS set to 111b then it is equivalent to the TS selecting ETRF as the input 11 2 3 4 Encoder mode Setting the SMS to 001b 010b 011b will enable the encoder mode Enabl...

Page 115: ...unctionality and implementation The complex functions of a general purpose timer are implemented by manipulating the timer s compare capture channel clock input circuitry and counter and peripheral components The clock input to the timer can be derived from multiple clock sources including the input to the compare capture channel The operation 0 1 01 10 11 TI1F Edge detector ICF 3 0 TIMx_CHCTLR1 T...

Page 116: ...ture register Set the CC1E bit 6 Configure the CCxIE and CCxDE bits as needed to determine whether to allow enable interrupts or DMA This completes the comparison capture channel configuration When a captured pulse is input to TI1 the value of the core counter CNT is recorded in the compare capture register CC1IF is set and the CCIOF bit is set when CC1IF has been set before If the CC1IE bit is se...

Page 117: ...d to use PWM mode 1 or mode 2 set the OCxPE bit to enable the preload register and finally set the ARPE bit to enable the automatic reload of the preload register The value of the preload register can only be sent to the shadow register when an update event occurs so the UG bit needs to be set to initialize all registers before the core counter starts counting In PWM mode the core counter and the ...

Page 118: ...m the core counter To use the encoder set the SMS field to 001b count only on TI2 edge 010b count only on TI1 edge or 011b count on both TI1 and TI2 edges connect the encoder to the input of the comparison capture channels 1 and 2 and set a reload value counter value which can be set to a larger value When in encoder mode the internal compare capture register prescaler repeat count register etc of...

Page 119: ...0000010 TIM2 interrupt status register 0x0000 R16_TIM2_SWEVGR 0x40000014 TIM2 event generation register 0x0000 R16_TIM2_CHCTLR1 0x40000018 TIM2 compare capture control register1 0x0000 R16_TIM2_CHCTLR2 0x4000001C TIM2 compare capture control register2 0x0000 R16_TIM2_CCER 0x40000020 TIM2 compare capture enable register 0x0000 R16_TIM2_CNT 0x40000024 TIM2 counter 0x0000 R16_TIM2_PSC 0x40000028 TIM2...

Page 120: ...alignment mode 2 The counter counts up and down alternately The output compare interrupt flag bit of the channel configured as output CCxS 00 in the CHCTLRx register is set only when the counter counts up 11 Central alignment mode 3 The counter counts up and down alternately The output compare interrupt flag bit of the channel configured as output CCxS 00 in the CHCTLRx register is set when the co...

Page 121: ...Reserved Bit Name Access Description Reset value 15 8 Reserved RO Reserved 0 7 TI1S RW TI1 selection 1 TIMx_CH1 TIMx_CH2 and TIMx_CH3 pins connected to TI1 input after heterodyning 0 TIMx_CH1 pin is connected directly to TI1 input 0 6 4 MMS RW Master mode selection These 3 bits are used to select the synchronization information TRGO sent to the slave timer in master mode The possible combinations ...

Page 122: ...ing edge 0 14 ECE RW External clock mode 2 enabled selection 1 Enables external clock mode 2 0 Disable external clock mode 2 Note 1 Slave mode can be used simultaneously with external clock mode 2 reset mode gated mode and trigger mode however TRGI cannot be connected to ETRF in this case TS bit cannot be 111b Note 2 When both external clock mode 1 and external clock mode 2 are enabled the externa...

Page 123: ...R3 111 External trigger input ETRF The above only changes when SMS is 0 0 3 Reserved RO Reserved 0 2 0 SMS RW Input mode selection field Selects the clock and trigger mode of the core counter 000 driven by the internal clock CK_INT 001 encoder mode 1 where the core counter increments or decrements the count at the edge of TI2FP2 depending on the level of TI1FP1 010 encoder mode 2 where the core co...

Page 124: ...equest enable bit of capture channel 1 1 allows comparison of DMA requests for capture channel 1 0 Disable comparison of DMA requests for capture channel 1 0 8 UDE RW Updated DMA request enable bit 1 DMA requests that allow updates 0 DMA requests for updates are disabled 0 7 Reserved RO Reserved 0 6 TIE RW Trigger the interrupt enable bit 1 Enables triggering of interrupts 0 Trigger interrupt is d...

Page 125: ... mode 1 Trigger event generation 0 No trigger event is generated 0 5 Reserved RO Reserved 0 4 CC4IF WO Compare capture channel 4 interrupt flag bits 0 3 CC3IF WO Compare capture channel 3 interrupt flag bits 0 2 CC2IF WO Compare capture channel 2 interrupt flag bits 0 1 CC1IF WO Compare capture channel 1 interrupt flag bits If the compare capture channel is configured in output mode this bit is se...

Page 126: ...pare capture channel 1 is configured as output set the CC1IF bit Generate the corresponding interrupts and DMAs if they are enabled If compare capture channel 1 is configured as input the current core counter value is captured to compare capture register 1 set the CC1IF bit and generate the corresponding interrupts and DMAs if they are enabled If CC1IF is already set set the CC1OF bit 0 No action ...

Page 127: ...apture register 1 100 Forced to invalid level Forces OC1REF to low 101 Force to valid level Force OC1REF to high 110 PWM mode 1 When counting up channel 1 is invalid level once the core counter is greater than the value of the compare capture register otherwise it is valid level when counting down channel 1 is valid level once the core counter is greater than the value of the compare capture regis...

Page 128: ... an output 01 comparison capture channel 2 is configured as an input and IC2 is mapped on TI2 10 comparison capture channel 2 is configured as an input and IC2 is mapped onTI1 11 Compare Capture Channel 2 is configured as an input and IC2 is mapped on TRC This mode works only when the internal trigger input is selected by the TS bit Note Compare Capture Channel 2 is writable only when the channel ...

Page 129: ...nnel is configured as an input and IC1 is mapped on TRC This mode works only when the internal trigger input is selected by the TS bit Note CC1S is writable only when the channel is off CC1E is 0 0 7 4 IC1F RW Input capture filter 1 configuration field 0 3 2 IC1PSC RW Compare the capture channel 1 prescaler configuration field 0 1 0 CC1S RW Compare capture channel 1 input selection fields 0 11 4 8...

Page 130: ...R Offset address 0x20 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CC4P CC4E Reserved CC3P CC3E Reserved CC2P CC2E Reserved CC1P CC1E Bit Name Access Description Reset value 15 14 Reserved RO Reserved 0 13 CC4P RW Compare the capture channel 4 output polarity setting bit 0 12 CC4E RW Compare capture channel 4 output enable bit 0 11 10 Reserved RO Reserved 0 9 CC3P RW Compare the capture channel ...

Page 131: ... 15 0 will be loaded into the counter read section 10 2 4 for when ATRLR acts and updates the counter stops when ATRLR is empty 0xFFF F 11 4 13 Compare capture register 1 TIM2_CH1CVR Offset address 0x34 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH1CVR 15 0 Bit Name Access Description Reset value 15 0 CH1CVR RW Compare the value of capture register channel 1 0 11 4 14 Compare capture register 2 TIM2_CH...

Page 132: ... 8 7 6 5 4 3 2 1 0 Reserved DBL 4 0 Reserved DBA 4 0 Bit Name Access Description Reset value 15 13 Reserved RO Reserved 0 12 8 DBL RW The length of the DMA continuous transmission the actual value of which is the value of this field 1 0 7 5 Reserved RO Reserved 0 4 0 DBA RW These bits define the offset of the DMA in continuous mode from the address where control register 1 is located 0 11 4 18 DMA...

Page 133: ...ing the first bit shifted out is the least significant bit and each data frame starts with a low start bit then the transmitter sends an eight or nine bit data word depending on the TransmitDataRegister TransmitShiftRegister ReceiveDataRegister ReceiveDataRegister PWDATA Write CPUorDMA CPUorDMA Read PRDATA DATAREGISTER DATAR TX RX SW_RX Connectwith RXInternally IrDA SIR ENDEC BLOCK Hardware flow c...

Page 134: ... has errors the waveform in the line generated by the change Peripheral module receiver is a certain receiving tolerance when the sum of the above three aspects of the total deviation is less than the module s tolerance limit the total deviation does not affect the transmission and reception The tolerance limitof the module is affected by whether to use fractional baud rate and M bit data field wo...

Page 135: ...ontrol registers 2 and 3 R16_USARTx_CTLR2 and R16_USARTx_CTLR3 After setting to half duplex mode you need to set the IO port of TX to floating input or open drain output high mode With TE set the data will be sent out as soon as it is written to the data register Special attention should be paid to the fact that the half duplex mode may cause bus conflicts when multiple devices use a single bus to...

Page 136: ...agram In smart card mode the waveform output from the CK pin when enabled has nothing to do with communication it simply clocks the smart card with the value of the APB clock followed by a five bit settable clock division twice the value of the PSC up to 62 divisions 12 7 IrDA The USART module supports control of IrDA infrared transceivers for physical layer communication The LINEN STOP CLKEN SCEN...

Page 137: ...SART_DATAR 0x40013804 UASRT data register 0x000000XX R32_USART_BRR 0x40013808 UASRT baud rate register 0x00000000 R32_USART_CTLR1 0x4001380C UASRT control register 1 0x00000000 R32_USART_CTLR2 0x40013810 UASRT control register 2 0x00000000 R32_USART_CTLR3 0x40013814 UASRT control register 3 0x00000000 R32_USART_GPR 0x40013818 UASRT protection time and prescaler register 0x00000000 12 10 1 USART St...

Page 138: ...f the data register clears this bit It is also possible to clear the bit by writing a 0 directly 1 Data received and able to be read out 0 The data has not been received 0 4 IDLE RO Bus idle flag When the bus is idle this bit will be set by hardware If IDLEIE is already set the corresponding interrupt will be generated The operation of reading the status register and then reading the data register...

Page 139: ... set previously then this bit being set generates a corresponding interrupt 1 A parity error 0 No inspection error 0 12 10 2 USART Data register USART_DATAR Offset address 0x04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DR 8 0 Bit Name Access Description Reset value 31 9 Reserved RO Reserved 0 8 0 DR RW Data register This register is act...

Page 140: ...ion is completed 0 8 PEIE RW Parity check interrupt enable bit This bit indicates that parity check error interrupts are allowed 0 7 TXEIE RW TXE interrupt enable This bit indicates that a TXE interrupt is allowed to be generated 0 6 TCIE RW Transmit completion interrupt enable This bit indicates that the transmit completion interrupt is allowed to be generated 0 5 RXNEIE RW RXNE interrupt enable ...

Page 141: ... Clock polarity This bit allows the user to select the polarity of the clock output on the CK pin in synchronous mode It works in conjunction with the CPHA bit to produce the desired clock data relationship 0 Steady low value on CK pin outside transmission window 1 Steady high value on CK pin outside transmission window Note This bit cannot be modified after enabling transmit 0 9 CPHA RW Clock pha...

Page 142: ... 2 1 0 Reserved CTSI E CTSE RTSE DMA T DMA R SCE N NAC K HDS EL IRLP IREN EIE Bit Name Access Description Reset value 31 11 Reserved RO Reserved 0 10 CTSIE RW CTS interrupt enable bit when this bit is set an interrupt will be generated when CTS is set 0 9 CTSE RW CTS enable bit setting this bit will enable CTS flow control 0 8 RTSE RW RTS enable bit setting this bit will enable RTS flow control 0 ...

Page 143: ...his bit field gives the Guard time value in terms of number of baud clocks This is used in Smartcard mode The Transmission Complete flag is set after this guard time value 0 7 0 PSC RW Prescaler value field In IrDA Low power mode the source clock is divided by this value all 8 bits valid with a value of 0 indicating retention In normal IrDA mode this bit can only be set to 1 In smartcard mode the ...

Page 144: ...one of the following four modes at the same time master device transmit mode master device receive mode slave device transmit mode and slave device receive mode the I2C module works in slave mode by default and automatically switches to master mode when a start condition is generated and to slave mode when arbitration is lost or a stop signal is generated the I2C module supports multi master funct...

Page 145: ...ader sequence the header sequence is 11110xx0b where the xx bits are the top two bits of the 10 bit address After sending the header sequence the ADD10 bit of the status register will be set and if the ITEVTEN bit has been set an interrupt will be generated at this time the R16_I2Cx_STAR1 register should be read and the ADD10 bit cleared after writing the second address byte to the data register T...

Page 146: ...l receive data from the SDA line and write it into the data register via the shift register After each byte if the ACK bit is set the I2C module will send an answer low and the RxNE bit will be set and an interrupt will be generated if ITEVTEN and ITBUFEN are set If RxNE is set and the original data is not read before the new data is received the BTF bit will be set and SCL will remain low until t...

Page 147: ...mes it is a restart signal and starts waiting for an address or stop signal if it is a stop signal it operates ahead of normal stop conditions In master mode the hardware does not release the bus while not affecting the current transfer and it is up to the user code to decide whether to abort the transfer 13 5 2 Acknowledge failure AF An answer error will be generated when the I2C module detects a...

Page 148: ...ion mode where the host provides the clock and supports multiple masters and slaves 2 Two wire communication architecture with an optional warning line for SMBus 3 Both support 7 bit address format There are also differences between SMBus and I2C 1 I2C supports speeds up to 400 KHz while SMBus supports up to 100 KHz and SMBus has a minimum speed limit of 10 KHz 2 A timeout will be reported when th...

Page 149: ...the number of data transfers set in the DMA controller has been completed the DMA controller sends an end of transfer EOT EOT_1 signal to the I2C interface A DMA interrupt will be generated if the interrupt is allowed l Reception using DMA DMA receive mode can be performed after setting DMAEN in the CTLR2 register When using DMA receive DMA transfers the data in the data register to the preset mem...

Page 150: ...DDR2 0x4000540C I2C address register 2 0x0000 R16_I2C_DATAR 0x40005410 I2C data register 0x0000 R16_I2C_STAR1 0x40005414 I2C status register 1 0x0000 R16_I2C_STAR2 0x40005418 I2C status register 2 0x0000 R16_I2C_CKCFGR 0x4000541C I2C clock register 0x0000 13 11 1 I2C Control register 1 I2C1_CTLR1 Offset address 0x00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWR ST Reserved PEC POS ACK STOP STAR T NOS ...

Page 151: ...it This bit is set and cleared by software cleared by hardware when a Stop condition is detected set by hardware when a timeout error is detected In Master mode 1 Stop generation after the current byte transfer or after the current Start condition is sent 0 No Stop generation In Slave mode 1 Release the SCL and SDA lines after the current byte transfer 0 No Stop generation 0 8 START RW Start gener...

Page 152: ... bit Set this bit to enable event interrupt This interrupt will be generated under the following conditions SB 1 Master mode ADDR 1 Master slave mode ADDR10 1 Master mode STOPF 1 Slave mode BTF 1 but no TxE or RxEN events TxE event to 1 if ITBUFEN 1 RxNE event to 1if ITBUFEN 1 0 8 ITERREN RW Error interrupt enable bit Set to allow error interrupts The interrupt will be generated under the followin...

Page 153: ...egister I2C_DATAR Offset address 0x10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DR 7 0 Bit Name Access Description Reset value 15 8 Reserved RO Reserved 0 7 0 DR RW Data register this field is used to store the received data or to store the data used to send to the bus 0 13 11 6 I2C Status register 1 I2C_STAR1 Offset address 0x14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PECE RR OVR AF A...

Page 154: ...served 0 4 STOPF RO Stop detection bit Cleared by software reading the SR1 register followed by a write in the CR1 register or by hardware when PE 0 1 Set by hardware when a Stop condition is detected on the bus by the slave after an acknowledge if ACK 1 0 No Stop condition detected 0 3 ADD10 RO 10 bit header sent bit Cleared by software reading the SR1 register followed by a write in the DR regis...

Page 155: ...atched with OAR2 0 Received address matched with OAR1 0 6 5 Reserved RO Reserved 0 4 GENCALL RO General call address bit Cleared by hardware after a Stop condition or repeated Start condition or when PE 0 1 General Call Address received when ENGC 1 0 No General Call 0 3 Reserved RO Reserved 0 2 TRA RO Transmitter receiver bit It is cleared by hardware after detection of Stop condition STOPF 1 repe...

Page 156: ...11 10 9 8 7 6 5 4 3 2 1 0 F S DUTY Reserved CCR 11 0 Bit Name Access Description Reset value 15 F S RW Master mode selection bit 1 Fm mode I2C 0 Sm mode I2C 0 14 DUTY RW Duty cycle of high level time over low level time in Fm 1 36 0 33 3 0 13 12 Reserved RO Reserved 0 11 0 CCR RW Clock control register in Fm Sm mode 0 ...

Page 157: ...ock diagram As can be seen from Figure 14 1 the four main SPI related pins are MISO M0SI SCK and NSS The MISO pin is the data input pin when the SPI module is operating in Master mode and the data output pin when it is operating in Slave mode the MOSI pin is the data output pin when it is operating in Master mode and the data input pin when it is operating in Slave mode the SCK is the clock pin th...

Page 158: ...PHA is not set to indicate that the SPI module samples data on the first edge of the clock and the data is latched and CPOL indicates whether the clock is held high or low when there is no data See Figure 14 2 below for details Figure 14 2 SPI Mode The host and device need to be set to the same SPI mode and the SPE bit needs to be cleared before configuring the SPI mode the DEF bit determines whet...

Page 159: ...mple edge the RXNE bit is set the bytes received by the shift register are transferred to the receive buffer and the read operation of the read data register can obtain the data in the receive buffer If RXNEIE is set before RXNE is set then an interrupt is generated 14 2 4 Simplex mode The SPI interface can operate in half duplex mode where the master device uses the MOSI pin and the slave device ...

Page 160: ... respectively In addition to the above three errors will also generate interrupts namely MODF OVR and CRCERR after enabling the ERRIE bit these three errors will also generate error interrupts 14 3 Register description Table 14 1 SPI related registers list Name Access address Description Reset value R16_SPI_CTLR1 0x40013000 SPI Control register1 0x0000 R16_SPI_CTLR2 0x40013004 SPI Control register...

Page 161: ...he NSS pins 0 Hardware control NSS pins 0 8 SSI RW Internal slave select bit with SSM set this bit determines the level of the NSS pin 1 NSS is high 0 NSS is low 0 7 Reserved RO Reserved 0 6 SPE RW SPI enable bit 1 Enable SPI 0 Disable SPI 0 5 3 BR RW Baud rate setting field this field cannot be modified during communication 000 FPCLK 2 001 FPCLK 4 010 FPCLK 8 011 FPCLK 16 100 FPCLK 32 101 FPCLK 6...

Page 162: ...bit 1 Enable Rx buffer DMA 0 Disable Rx buffer DMA 0 14 3 3 SPI Status register SPI1_STATR Offset address 0x08 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BSY OVR MODF CRC ERR UDR CHSID TXE RXNE Bit Name Access Description Reset value 15 8 Reserved RO Reserved 0 7 BSY RO Busy flag This flag is set and cleared by hardware 1 SPI is busy in communication or Tx buffer is not empty 0 SPI or I2 S not...

Page 163: ...peration of different areas where the read pairs use the receive buffer and the write pairs correspond to the send buffer Data can be received and sent in 8 or 16 bits and it is necessary to determine how many bits of data to use before transmission When using 8 bits for data transmission only the lower 8 bits of the data registers are used and the higher 8 bits are forced to 0 for reception using...

Page 164: ...ed CRC checksum of the bytes that have been sent out Setting CRCEN resets this register The calculation method uses the polynomial used in CRCPOLY 8 bit mode only the lower 8 bits are involved in the calculation while in 16 bit mode all 16 bits are involved It is necessary to read this register when BSY is 0 0 14 3 8 SPI High speed control register SPI1_HSCR Offset address 0x24 15 14 13 12 11 10 9...

Page 165: ...or to indicate the identity information All the above can be read accessed by 8 16 32 bit by the user 15 2 Register description Table 15 1 ESIG related registers list Name Access Address Description Reset value R16_ESIG_FLACAP 0x1FFFF7E0 Flash capacity register 0xXXXX R32_ESIG_UNIID1 0x1FFFF7E8 UID register 1 0xXXXXXXXX R32_ESIG_UNIID2 0x1FFFF7EC UID register 2 0xXXXXXXXX R32_ESIG_UNIID3 0x1FFFF7F...

Page 166: ...set value 31 0 U_ID 63 32 RO The 32 63 digits of UID X 15 2 4 UID register ESIG_UNIID3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 U_ID 95 80 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 U_ID 79 64 Bit Name Access Description Reset value 31 0 U_ID 95 64 RO The 64 95 digits of UID X ...

Page 167: ...ramming in single 2 byte mode and performs erase and whole erase operation in single 1K byte l Fast programming This method uses the page operation method recommended After a specific sequence of unlocking a single 64 byte programming and 64 byte erasure 1Kbyte erasure and whole piece erasure are performed 16 2 2 Security prevent illegal access read write erase l Page write protection l Read prote...

Page 168: ...9 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LATENCY Bit Name Access Description Reset value 31 2 Reserved RO Reserved 0 1 0 LATENCY RW Number of FLASH wait states 00 0 wait recommended 0 SYSCLK 24MHz 01 1 wait recommended 24 SYSCLK 48MHz Other Invalid 0 16 3 2 FPEC key register FLASH_KEYR Offset address 0x04 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 169: ... can switch to the user area 0 13 6 Reserved RO Reserved 0 5 EOP RW1 Indicates the end of the operation and write 1 clears 0 The hardware is set each time it is successfully erased or programmed 0 4 WRPRTERR RW1 Indicates a write protection error write 1 clear The hardware will set the address if it is programmed for write protection 0 3 1 Reserved RO Reserved 0 0 BUSY RO Indicates busy status 1 I...

Page 170: ...bled 0 9 OBWRE RW0 User selects word lock software clears 0 1 Indicates that the user select word can be programmed for operation It needs to be set by hardware after writing the correct sequence in FLASH_OBKEYR register 0 Re lock the user selection word after the software is cleared 0 8 Reserved RO Reserved 0 7 LOCK RW1 Lock Only 1 can be written When this bit is 1 it means that FPEC and FLASH_CT...

Page 171: ... Data byte 1 X 17 10 DATA0 Data byte 0 X 9 8 2 b11 7 Reserved RO Reserved X 6 5 CFGRSTT RO Configuration word reset delay time X 4 STANDY_ RST RO System reset control in Standby mode X 3 Reserved RO Reserved X 2 IWDG_SW RO Independent Watchdog IWDG hardware enable bit 1 1 RDPRT RO Read protection status 1 Indicates that the flash memory is currently read protected 1 0 OBERR RO Wrong choice of word...

Page 172: ... unlock the BOOT area KEY1 0x45670123 KEY2 0xCDEF89AB X 16 4 Flash memory operation flow 16 4 1 Read operations With direct addressing in the general address space any read operation of 8 16 32 bit data can access the contents of the flash module and get the corresponding data 16 4 2 Unlocking the flash memory After a system reset the flash controller FPEC and FLASH_CTLR registers are locked and i...

Page 173: ...half word 2 bytes Read EOP WRPRTERR to judge the programmingresult Read the programmed addressto check the written data Continue programming Over PG bit 0 LOCK bit 1 YES NO NO YES YES NO 1 Check the FLASH_CTLR register LOCK if it is 1 you need to execute the Unlock Flash operation 2 Set the PG bit of FLASH_CTLR register to 1 to enable the standard programming mode 3 Write the half word to be progr...

Page 174: ...rite the page header address of the selected erase to FLASH_ADDR register 4 Set the STAT bit of FLASH_CTLR register to 1 to initiate an erase action 5 Wait for the BYS bit to become 0 or the EOP bit of FLASH_STATR register to be 1 to indicate the end of erase and clear the EOP bit to 0 6 Read the data of the erased page for verification 7 Continue the standard page erase can repeat steps 3 5 and e...

Page 175: ...ming operations in progress 3 Check the FLASH_CTLR register FLOCK bit if it is 1 you need to execute the fast programming mode unlock operation 4 Set the FTPG bit of FLASH_CTLR register to enable the fast programming mode function 5 Set the BUFRST bit of FLASH_CTLR register to perform the operation of clearing the internal 64 byte buffer 6 Wait for the BYS bit to become 0 or the EOP bit of FLASH_S...

Page 176: ...protection 1 byte for configuration options and 2 bytes for storing user data and each bit has its inverse code bit for checksum during loading The following describes the structure and meaning of the select word information Table 16 3 32 bit selection word format division 31 24 23 16 15 8 7 0 Select word byte 1 inverse code Select word byte 1 Select word byte 0 inverse code Select word byte 0 Tab...

Page 177: ... set to 1 indicating that the user select word can be erased and programmed It can be locked again by clearing the OBWRE bit of FLASH_CTLR register to 0 by software Unlock sequence 1 Write KEY1 0x45670123 to FLASH_OBKEYR register 2 Write KEY2 0xCDEF89AB to FLASH_OBKEYR register Note User selected word operation requires unlocking the LOCK and OBWRE layers 16 5 2 User selected word programming Only...

Page 178: ...FLASH_CTLR register to 1 to enable the user select word erase 5 Wait for the BYS bit to become 0 or the EOP bit of FLASH_STATR register to be 1 to indicate the end of erase and clear the EOP bit to 0 6 Read and erase the address data checksum 7 End to clear the OBER bit to 0 16 5 4 Unprotecting reads Whether the flash memory is read protected or not is determined by the user selected word Read the...

Page 179: ...figure OPA_NSEL to select the negative input pin of the OPA 17 2 Register description Table 17 1 EXTEND related registers list Name Access address Description Reset value R32_EXTEN_CTR 0x40023800 Configure extended control registers 0x00000A00 17 2 1 Configuring the extended control register EXTEND_CTR Offset address 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved OP A_ PSE L OP A_ N...

Page 180: ...03 Reference Manual http wch cn V1 3 180 6 LKUPEN RW LOCKUP monitoring function 1 Enabled performs a reset and sets LOCKUP_RESET when a lock up occurs on the system 0 Not enabled 0 5 0 Reserved RO Reserved 0 ...

Page 181: ...ccess Description Reset value 31 6 Reserved RW Reserved 0 5 TIM2_STOP RW Timer 2 debug stop bit The counter stops when the core enters the debug state 1 Timer 2 s counter stops working 0 Timer 2 s counter is still working normally 0 4 TIM1_STOP RW Timer 1 debug stop bit The counter stops when the kernel enters the debug state 1 Timer 1 s counter stops working 0 Timer 1 s counter is still working n...

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