MAX 10 Plus User
Manual
44
May 31, 2019
Chapter 5
RTL Example Codes
This chapter provides examples of advanced designs implemented by RTL on the MAX 10 Plus
board. These reference designs cover the features of peripherals connected to the FPGA, such as
PS/2 mouse, ADC/DAC application. All the associated files can be found in the directory
\Demonstrations of System CD. Note: The output files generated after compilation in Quartus II
e.g. .sof and .pof files, are saved in the folder "output_files" under the directory of demo project.
5.1
PS/2 Mouse Demonstration
We offer this simple PS/2 controller coded in Verilog HDL to demonstrate bidirectional
communication between PS/2 controller and the device, the PS/2 mouse. You can treat it as a
how-to basis and develop your own controller that could accomplish more sophisticated instructions,
like setting the sampling rate or resolution, which need to transfer two data bytes.
More information about the PS/2 protocol can be found on various websites.
◼
Introduction
PS/2 protocol uses two wires for bi-directional communication. One is the clock line and the other
one is the data line. The PS/2 controller always has total control over the transmission line, but it is
the PS/2 device which generates the clock signal during data transmission.
◼
Data Transmission from Device to the Controller
After the PS/2 mouse receives an enabling signal at stream mode, it will start sending out
displacement data, which consists of 33bits. The frame data is cut into three sections and each of
them contains a start bit (always zero), eight data bits (with LSB first), one parity check bit (odd
check), and one stop bit (always one).
The PS/2 controller samples the data line at the falling edge of the PS/2 clock signal. This is
implemented by a shift register, which consists of 33bits, but please be cautious with the clock
domain crossing problem.
◼
Data Transmission from the Controller to Device
When the PS/2 controller wants to transmit data to device, it first pulls the clock line low for more
than one clock cycle to inhibit the current transmission process or to indicate the start of a new
transmission process, which is usually called as inhibit state. It then pulls low the data line before
releasing the clock line. This is called the request state. The rising edge on the clock line formed by
the release action can also be used to indicate the sample time point as for a start bit. The device
will detect this succession and generates a clock sequence in less than 10ms time. The transmit data
consists of 12bits, one start bit (as explained before), eight data bits, one parity check bit (odd
check), one stop bit (always one), and one acknowledge bit (always zero).
