MAX 10 Plus User
Manual
15
May 31, 2019
Table 3-1 LED Indicators
Board Reference LED Name
Description
D13
5V Power
Illuminate when 5V power is active.
D14
2.5V Power
Illuminate when 2.5V power is active.
D16
1.2V Power
Illuminate when 1.2V power is active.
D6
CONF_DONE
Illuminate when configuration data is loaded into MAX 10 device
without error.
D7
JTAG_RX
Illuminate during data is uploaded from MAX 10 device to PC through
UB2.
D8
JTAG_TX
Illuminate during configuration data is loaded into MAX 10 device
from UB2.
TXD
TXD
Illuminate during transmitting data via USB.
RXD
RXD
Illuminate during receiving data via USB.
3.3
Clock Circuitry
shows the default frequency of all external clocks to the MAX 10 FPGA. A clock
generator is used to distribute clock signals with low jitter. The three 50MHz clock signals
connected to the FPGA are used as clock sources for user logic. One 25MHz clock signal is
connected to the clock input of Gigabit Ethernet Transceiver. One 24MHz clock signal is connected
to the clock inputs of USB microcontroller of USB Blaster II. One 28.63636MHz clock signal is
connected to the clock input of HDMI Receiver chip. The other 50MHz clock signal is connected to
MAX CPLD of USB Blaster II. One 10MHz clock signal is connected to the PLL1 and PLL3 of
FPGA, the outputs of these two PLLs can drive ADC clock. The associated pin assignment for
clock inputs to FPGA I/O pins is listed in
