MAX 10 Plus User
Manual
16
May 31, 2019
Figure 3-10 Block Diagram of the Clock Distribution on MAX 10 Plus
Table 3-2 Pin Assignment of Clock Inputs
Signal Name
FPGA Pin No.
Description
I/O Standard
MAX10_CLK1_50
PIN_N5
50MHz clock input
2.5V
MAX10_CLK2_50
PIN_V9
50MHz clock input
3.3V
MAX10_CLK3_50
PIN_N14
50MHz clock input
1.5V
ADC_CLK_10
PIN_M9
10MHz clock input
3.3V
3.4
Peripherals Connected to the FPGA
This section describes the interfaces connected to the FPGA. User can control or monitor different
interfaces with user logic from the FPGA.
3.4.1
User Push-buttons, Switches, LEDs
The board has five push-buttons connected to the FPGA, as shown in
MAX 10 devices
support Schmitt trigger input on all I/O pins. A Schmitt trigger feature introduces hysteresis to the
input signal for improved noise immunity, especially for signal with slow edge rate and act as
switch debounce in
for the push-buttons connected.
