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MAX 10 Plus User
Manual

37

www.terasic.com

May 31, 2019

Chapter 4

The MAX 10 Plus System Builder

This chapter introduces the MAX 10 Plus System Builder to help users get started in creating their
own projects in literally minutes. It also describes the design flow and includes an example for users
to get familiar with the tool.

4.1

Introduction

The MAX 10 Plus System Builder is a Windows-based utility. It is created to help users build a top
project for MAX 10 Plus within minutes. The generated Quartus II project files include:

•

Quartus II project file (.qpf)

•

Quartus II setting file (.qsf)

•

Top-level design file (.v)

•

Synopsis design constraints file (.sdc)

•

Pin assignment document (.htm)

The above files generated by the MAX 10 Plus System Builder can also prevent situations that are
prone to compilation error when users manually edit the top-level design file or place pin
assignment. The common mistakes that users encounter are:

•

Board is damaged due to incorrect bank voltage setting or pin assignment.

•

Board is malfunctioned because of wrong device chosen, declaration of pin location, or the
direction is incorrect/forgotten.

•

Performance degradation due to improper pin assignment.

4.2

General Design Flow

The design flow of building a Quartus II project for MAX 10 Plus using the MAX 10 Plus System
Builder is illustrated in

. It gives users an overview about the steps, starting from

launching the System Builder to configuring the FPGA. The left-hand side of the chart can be done
within  minutes.  After  users  enter  the  design  requirements,  the  MAX  10  Plus  System  Builder  will
generate  Quartus  II  project  files,  Quartus  II  setting  file,  top-level  design  file,  Synopsis  design
constraint file, and the pin assignment document.

The  top-level  design  file  contains  a  top-level  Verilog  HDL  wrapper  for  users  to  add  their  own
design/logic. The Quartus  II setting file contains information such as FPGA device type, top-level
pin  assignment,  and  the  I/O  standard  for  each  user-defined  I/O  pin.  These  files  can  be  modified
according  to  the  project  requirements.  After  the  compilation  is  successful,  users  can  download
the .sof file to the development board via JTAG interface using the Quartus II programmer.

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Summary of Contents for MAX10-Plus

Page 1: ...MAX 10 Plus User Manual 1 www terasic com May 31 2019 ...

Page 2: ... 1 Configuration of MAX 10 FPGA on MAX 10 Plus 10 3 2 Board Status Elements 14 3 3 Clock Circuitry 15 3 4 Peripherals Connected to the FPGA 16 3 4 1 User Push buttons Switches LEDs 16 3 4 2 7 segment Displays 19 3 4 3 Power Monitor 20 3 4 4 2x6 TMD Expansion Header 21 3 4 5 24 bit Audio CODEC 22 3 4 6 Two Analog Input SMA Connectors 23 3 4 7 DDR3 Memory 23 3 4 8 QSPI Flash 25 3 4 9 Ethernet 26 3 4...

Page 3: ...Plus System Builder 38 Chapter 5 RTL Example Codes 44 5 1 PS 2 Mouse Demonstration 44 5 2 ADC Potentiometer 46 5 3 DAC Demonstration 48 5 4 ADC MIC LED Demonstration 51 Chapter 6 NIOS Based Example Codes 54 6 1 Power Monitor 54 6 2 UART to USB Control LED 58 6 3 SD Card Audio Demonstration 61 6 4 DDR3 SDRAM Test by Nios II 65 6 5 Ethernet Socket server 68 6 6 Digital Accelerometer Demonstration 75...

Page 4: ...nd reference designs for developing a wide range of audio video and many other exciting applications The fully integrated kit allows developers to rapidly customize their processor and IP to suit their specific needs rather than constraining their software around the fixed feature set of the processor The all in one embedded solution the MAX 10 Plus making the best use of the parallel nature of FP...

Page 5: ...ssociated with MAX 10 Plus including the user manual system builder reference designs and device datasheets Users can download this system CD from the link http max10 plus terasic com cd 1 3 Getting Help Here are the addresses where you can get help if you encounter any problems Terasic Technologies 9F No 176 Sec 2 Gongdao 5th Rd East Dist Hsinchu City 30070 Taiwan Email support terasic com Tel 88...

Page 6: ...omponents Figure 2 1 MAX 10 Plus Development Board top view The MAX 10 Plus board has many features that allow users to implement a wide range of designed circuits from simple circuits to various multimedia projects The following hardware is provided on the board Intel MAX 10 10M50DAF484C6G device USB Blaster II onboard for programming JTAG Mode 256MB DDR3 SDRAM 64Mx16 and 128Mx8 64MB QSPI Flash M...

Page 7: ...ne ambient light sensor One humidity and temperature sensor One accelerometer One external 16bit digital to analog converter DAC device with SMA output Potentiometer input to ADC Two MAX 10 FPGAADC SMA inputs One 2x10 ADC header with 16 analog inputs connected to MAX10 ADCs 2 2 Block Diagram of the MAX 10 Plus Figure 2 2 is the block diagram of the board All the connections are established through...

Page 8: ...evice 256MB DDR3 SDRAM 64Mx16 and 128Mx8 512MB QSPI Flash Micro SD card socket Communication and Expansion Header Gigabit Ethernet PHY with RJ45 connector UART to USB USB Mini B connector PS 2 mouse keyboard connector 2x6 TMD Terasic Mini Digital Expansion Header Audio 24 bit CD quality audio CODEC with line in line out jacks Video Input HDMI RX incorporates HDM v1 4a features including 3D video s...

Page 9: ...AX 10 Plus User Manual 9 www terasic com May 31 2019 Ten red user LEDs Two 7 segment displays Sensors Ambient light sensor Humidity and temperature sensor Accelerometer Power monitor Power 5V 3A DC input ...

Page 10: ...g internal flash Before internal configuration you need to program the configuration data into the configuration flash memory CFM which provides non volatile storage for the bit stream The information is retained within CFM even if the MAX 10 Plus is turned off When the board is powered on the configuration data in the CFM is automatically loaded into the MAX 10 FPGA JTAG Chain on MAX 10 Plus The ...

Page 11: ...11 www terasic com May 31 2019 Figure 3 2 Detect FPGA Device in JTAG Mode 2 Select detected device associated with the board as circled in Figure 3 3 Figure 3 3 Select 10M50DAES Device 3 FPGA is detected as shown in Figure 3 4 ...

Page 12: ...asic com May 31 2019 Figure 3 4 FPGA Detected in Quartus Programmer 4 Right click on the FPGA device and open the sof file to be programmed as highlighted in Figure 3 5 Figure 3 5 Open the sof File to be Programmed into the FPGA Device ...

Page 13: ...programmed as shown in Figure 3 6 Figure 3 6 Select the sof File to be Programmed into the FPGA Device 6 Click Program Configure check box and then click Start button to download the sof file into the FPGA device as shown in Figure 3 7 Figure 3 7 Program sof File into the FPGA Device ...

Page 14: ... is powered up Please refer to Chapter 7 Programming the Configuration Flash Memory for the basic programming instruction on the configuration flash memory CFM Figure 3 8 High Level Overview of Internal Configuration for MAX 10 Devices 3 2 Board Status Elements In addition to the 10 LEDs that FPGA device can control there are 4 indicators which can indicate the board status See Figure 3 9 please r...

Page 15: ...data via USB 3 3 Clock Circuitry Figure 3 10 shows the default frequency of all external clocks to the MAX 10 FPGA A clock generator is used to distribute clock signals with low jitter The three 50MHz clock signals connected to the FPGA are used as clock sources for user logic One 25MHz clock signal is connected to the clock input of Gigabit Ethernet Transceiver One 24MHz clock signal is connected...

Page 16: ... input 3 3V 3 4 Peripherals Connected to the FPGA This section describes the interfaces connected to the FPGA User can control or monitor different interfaces with user logic from the FPGA 3 4 1 User Push buttons Switches LEDs The board has five push buttons connected to the FPGA as shown in Figure 3 11 MAX 10 devices support Schmitt trigger input on all I O pins A Schmitt trigger feature introduc...

Page 17: ...3 13 These switches are used as level sensitive data inputs to a circuit Each switch is connected directly and individually to the FPGA When the switch is set to the DOWN position towards the edge of the board it generates a low logic level to the FPGA When the switch is set to the UP position a high logic level is generated to the FPGA Pushbutton released Pushbutton depressed Before Debouncing Sc...

Page 18: ...vel or low level to turn the LED on or off respectively Figure 3 14 shows the connections between LEDs and MAX 10 FPGA Table 3 3 Table 3 4 and Table 3 5 list the pin assignment of user push buttons switches and LEDs Figure 3 14 Connections between the LEDs and the MAX 10 FPGA Table 3 3 Pin Assignment of Push buttons Signal Name FPGA Pin No Description I O Standard KEY 0 PIN_T22 Push button 0 1 5V ...

Page 19: ...tion I O Standard LEDR 0 PIN_C2 LEDR 0 3 3V LEDR 1 PIN_B3 LEDR 1 3 3V LEDR 2 PIN_A3 LEDR 2 3 3V LEDR 3 PIN_C3 LEDR 3 3 3V LEDR 4 PIN_A4 LEDR 4 3 3V LEDR 5 PIN_B4 LEDR 5 3 3V LEDR 6 PIN_C4 LEDR 6 3 3V LEDR 7 PIN_B5 LEDR 7 3 3V LEDR 8 PIN_C5 LEDR 8 3 3V LEDR 9 PIN_D5 LEDR 9 3 3V 3 4 2 7 segment Displays The MAX 10 Plus has two 7 segment displays These displays are paired to display numbers in variou...

Page 20: ...nt Digit 1 1 3 3V HEX1 2 PIN_D8 Seven Segment Digit 1 2 3 3V HEX1 3 PIN_D10 Seven Segment Digit 1 3 3 3V HEX1 4 PIN_E10 Seven Segment Digit 1 4 3 3V HEX1 5 PIN_H11 Seven Segment Digit 1 5 3 3V HEX1 6 PIN_E6 Seven Segment Digit 1 6 3 3V 3 4 3 Power Monitor The MAX 10 Plus has implemented three power monitor chips to monitor the FPGA core power and VCCIO power voltage and current Figure 3 16 shows t...

Page 21: ...V 3 4 4 2x6 TMD Expansion Header The board has one 2x6 TMD Terasic Mini Digital expansion header The TMD header has 8 digital GPIO user pins connected to the MAX 10 FPGA two 3 3V power pins and two ground pins There are two Transient Voltage Suppressor diode arrays used to implement ESD protection for 8 GPIO user pins Figure 3 17 shows the connection between the TMD header and MAX 10 FPGA Table 3 ...

Page 22: ...z to 192KHz The connection of the audio circuitry to the FPGA is shown in Figure 3 18 and the associated pin assignment to the FPGA is listed in Table 3 9 More information about the TLV320AIC3254 CODEC is available in its datasheet which can be found on the manufacturer s website or in the directory Datasheet Audio CODEC of MAX 10 Plus System CD Figure 3 18 Connections between the FPGA and Audio C...

Page 23: ...he analog inputs are amplified and translated by Texas Instruments INA159 gain of 0 2 level translation difference amplifier then the amplifier s outputs are fed to dedicated single ended analog input pins for MAX 10 build in ADC1 and ADC2 respectively With the amplifiers the analog input of two SMAs support from 6 25V to 6 25V range Figure 3 19 shows the connection of SMA connectors to the FPGA F...

Page 24: ... Class I DDR3_A 7 PIN_Y20 DDR3 Address 7 SSTL 15 Class I DDR3_A 8 PIN_C22 DDR3 Address 8 SSTL 15 Class I DDR3_A 9 PIN_D22 DDR3 Address 9 SSTL 15 Class I DDR3_A 10 PIN_J14 DDR3 Address 10 SSTL 15 Class I DDR3_A 11 PIN_E22 DDR3 Address 11 SSTL 15 Class I DDR3_A 12 PIN_G22 DDR3 Address 12 SSTL 15 Class I DDR3_A 13 PIN_D19 DDR3 Address 13 SSTL 15 Class I DDR3_A 14 PIN_C20 DDR3 Address 14 SSTL 15 Class...

Page 25: ...6 PIN_T19 DDR3 Data 15 SSTL 15 Class I DDR3_DQ 17 PIN_R20 DDR3 Data 15 SSTL 15 Class I DDR3_DQ 18 PIN_R15 DDR3 Data 15 SSTL 15 Class I DDR3_DQ 19 PIN_P15 DDR3 Data 15 SSTL 15 Class I DDR3_DQ 20 PIN_P19 DDR3 Data 15 SSTL 15 Class I DDR3_DQ 21 PIN_P14 DDR3 Data 15 SSTL 15 Class I DDR3_DQ 22 PIN_R14 DDR3 Data 15 SSTL 15 Class I DDR3_DQ 23 PIN_P20 DDR3 Data 15 SSTL 15 Class I DDR3_DQS_n 0 PIN_K15 DDR3...

Page 26: ..._DATA 3 PIN_AA20 FLASH Data 3 3 3V FLASH_DCLK PIN_AB17 FLASH Data Clock 3 3V FLASH_NCSO PIN_AB21 FLASH Chip Enable 3 3V FLASH_RESET_n PIN_AB20 FLASH Chip Reser 3 3V 3 4 9 Ethernet The board supports Gigabit Ethernet transfer by an external Marvell 88E1111 PHY chip The 88E1111 chip with integrated 10 100 1000 Mbps Gigabit Ethernet transceiver support GMII MII RGMII TBI MAC interfaces Figure 3 22 sh...

Page 27: ... PIN_A8 GMII and MII receive data valid 2 5V NET_RX_ER PIN_B8 GMII and MII receive data valid 2 5V NET_RX_D 0 PIN_A10 GMII and MII receive data 0 2 5V NET_RX_D 1 PIN_B10 GMII and MII receive data 1 2 5V NET_RX_D 2 PIN_A11 GMII and MII receive data 2 2 5V NET_RX_D 3 PIN_B11 GMII and MII receive data 3 2 5V NET_RX_CLK PIN_J10 GMII and MII receive clock 3 3V NET_RST_n PIN_C14 Hardware Reset Signal 2 ...

Page 28: ... MAX 10 device Figure 3 23 Connection between the MAX 10 FPGA and HDMI Receiver Table 3 13 Pin Assignment of HDMI RX Signal Name FPGA Pin No Description I O Standard HDMI_RX_D0 PIN_AA9 Video Pixel Output Port 3 3V HDMI_RX_D1 PIN_AB9 Video Pixel Output Port 3 3V HDMI_RX_D2 PIN_Y10 Video Pixel Output Port 3 3V HDMI_RX_D3 PIN_AA10 Video Pixel Output Port 3 3V HDMI_RX_D4 PIN_AB10 Video Pixel Output Po...

Page 29: ...PIN_R13 I2C Clock 3 3V HDMI_I2C_SDA PIN_P13 I2C Data 3 3V HDMI_MCLK PIN_R12 Audio Master Output Clock 3 3V HDMI_LRCLK PIN_V11 Audio Left Right Clock 3 3V HDMI_SCLK PIN_W8 Audio Serial Output Clock 3 3V HDMI_AP PIN_W9 Audio Output Pin 3 3V HDMI_RX_RESET_n PIN_AA13 System Reset Input 3 3V 3 4 11 2x10 ADC Header The board has a 2x10 ADC header with sixteen analog inputs connected to FPGA ADC1 and ADC...

Page 30: ...be pre amplified by audio operational amplifier OPA1612 then fed into the FPGA ADC Figure 3 24 shows the connection of on board microphone and MAX 10 FPGA 3 4 14 PS 2 Serial Port The MAX 10 Plus comes with a standard PS 2 interface and a connector for a PS 2 keyboard or mouse Figure 3 25 shows the connection of PS 2 circuit to the FPGA Users can use the PS 2 keyboard and mouse on the MAX 10 Plus s...

Page 31: ...PS2_DAT2 PIN_R3 PS 2 Data reserved for second PS 2 device 3 3V 3 4 15 Digital to Analog Converter DAC The board provides a Texas Instruments DAC8551 16 bit digital to analog converter DAC It is a small low power voltage output DAC The DAC8551 used a versatile 3 wire serial interface that operates at clock rates to 30MHz and is compatible with standard SPI QSPI Microwire and DSP interfaces The anal...

Page 32: ...mmunication with the MAX 10 FPGA This interface doesn t support HW flow control signals The physical interface is implemented by UART USB onboard bridge from a FT232R chip to the host with an USB Mini B connector More information about the chip is available on the manufacturer s website or in the directory Datasheets UART TO USB of MAX 10 Plus system CD Figure 3 28 shows the connections between th...

Page 33: ...ction of APDS 9301 to the MAX 10 FPGA Table 3 17 lists the Ambient Light Sensor pin assignments Figure 3 29 The Connections between the MAX 10 FPGA and Ambient Light Sensor Table 3 17 Pin Assignment of Ambient Light Sensor Signal Name FPGA Pin No Description I O Standard LSENSOR_SCL PIN_M1 I2C Serial Clock 3 3V LSENSOR_SDA PIN_T3 I2C Serial Data 3 3V LSENSOR_INT PIN_M2 Interrupt signal from Sensor...

Page 34: ...r sensor module ADXL345 commonly known as G sensor This G sensor is a small thin ultralow power assumption 3 axis accelerometer with high resolution measurement Digitalized output is formatted as 16 bit in two s complement and can be accessed through I2C interface The I2C address of accelerometer is 0xA6 0xA7 More information about this chip can be found in its datasheet which is available on manu...

Page 35: ...2 2 5V 3 4 20 Micro SD Card Socket The board supports Micro SD card interface with x4 data lines It serves not only an external storage for the HPS but also an alternative boot option for MAX 10 Plus Figure 3 32 shows signals connected between the HPS and Micro SD card socket Table 3 20 lists the pin assignment of Micro SD card socket to the MAX 10 FPGA Figure 3 32 Connections between the MAX 10 F...

Page 36: ... Manual 36 www terasic com May 31 2019 high efficiency power management for FPGAs and SoCs Figure 3 33 shows the power tree of MAX 10 Plus Note that the LCD interface are reserved Figure 3 33 Power Tree of MAX 10 Plus ...

Page 37: ... Board is malfunctioned because of wrong device chosen declaration of pin location or the direction is incorrect forgotten Performance degradation due to improper pin assignment 4 2 General Design Flow The design flow of building a Quartus II project for MAX 10 Plus using the MAX 10 Plus System Builder is illustrated in Figure 4 1 It gives users an overview about the steps starting from launching ...

Page 38: ...in details on how to use the MAX 10 Plus System Builder Install and Launch the MAX 10 Plus System Builder The MAX 10 Plus System Builder is located in the directory Tools SystemBuilder of the MAX 10 Plus System CD Users can copy the entire folder to a host PC without installing the utility After the execution of the MAX 10 Plus SystemBuilder exe on the host PC a window will pop up as shown in Figu...

Page 39: ...terasic com May 31 2019 Figure 4 2 The GUI of MAX 10 Plus System Builder Enter Project Name The project name entered in the circled area as shown in Figure 4 3 will be assigned automatically as the name of the top level design entity ...

Page 40: ... more onboard peripherals in the project as shown in Figure 4 4 If a component is enabled the MAX 10 Plus System Builder will automatically generate its associated pin assignment including the pin name pin location pin direction and I O standard Note The MIPI CS2 Camera and LCD Touch Panel interfaces are reserved users can choose to buy MAX 10 NEEK instead if needed these two interfaces ...

Page 41: ...m May 31 2019 Figure 4 4 List of onboard Peripherals in System Configuration Project Settings The MAX 10 Plus System Builder also provides the option to load a setting or save the current board configuration in cfg file as shown in Figure 4 5 ...

Page 42: ... May 31 2019 Figure 4 5 Manage Project Settings Project Generation When users press the Generate button as shown in Figure 4 6 the MAX 10 Plus System Builder will generate the corresponding Quartus II files and documents as listed in Table 4 1 ...

Page 43: ...n 1 Project name v Top level Verilog HDL file for Quartus II 2 Project name qpf Quartus II project file 3 Project name qsf Quartus II setting file 4 Project name sdc Synopsis design constraints file for Quartus II 5 Project name htm Pin assignment document Users can add custom logic into the project and compile the project in Quartus II to generate the SRAM Object File sof ...

Page 44: ...generates the clock signal during data transmission Data Transmission from Device to the Controller After the PS 2 mouse receives an enabling signal at stream mode it will start sending out displacement data which consists of 33bits The frame data is cut into three sections and each of them contains a start bit always zero eight data bits with LSB first one parity check bit odd check and one stop ...

Page 45: ...rrectly received After the power on cycle of the PS 2 mouse it enters into stream mode automatically and disable data transmit unless an enabling instruction is received Figure 5 1 shows the waveform while communication happening on two lines Figure 5 1 Waveform of Clock and Data Signals during Data Transmission Design Tools Quartus II v15 0 64 bit Demonstration Source Code Project directory ps2_m...

Page 46: ...ton right button and or middle button is pressed Table 5 1 Description of 7 segment Display and LED Indicators Indicator Name Description LEDR0 Left button press indicator LEDR1 Right button press indicator LEDR2 Middle button press indicator HEX0 Low byte of X Y displacement HEX1 High byte of X Y displacement 5 2 ADC Potentiometer Nowadays voltage and current monitors play a significant role in h...

Page 47: ... PLL It feeds into the ADC Hard IP in MAX10 device The analog voltage input comes from the VR controls the voltage level The control logic within the ADC Hard IP reads the digitized voltage data It then converts the data and displays the level value on two 7 segments Since none of the dot points of two 7 segments is connected to the MAX 10 so HEX1 and HEX0 shows the decimal point and the first dig...

Page 48: ...sistor POT1 with a screwdriver HEX1 and HEX0 will display the voltage value 5 3 DAC Demonstration This demonstration uses the 16 bit Digital to analog converter DAC built in the MAX 10 device to generate square wave in 8 difference frequencies The signal coming out of the SMA connector on MAX 10 Plus board is transmitted to the oscilloscope The oscilloscope will display the square wave in differen...

Page 49: ...river are installed on the host PC Connect the USB cable from the USB Blaster II port J8 to the host PC Plug in the 5V adapter to the MAX 10 Plus board and power it up Execute the demo batch file test bat from the directory dac_sma demo_batch Connect the probe of the oscilloscope to the DAC SMA OUT of the MAX 10 Plus board and adjust the display until the square wave is visible as Figure 5 6 and F...

Page 50: ...MAX 10 Plus User Manual 50 www terasic com May 31 2019 Figure 5 6 Use the Oscilloscope to Observe the Square Wave Figure 5 7 Probe DAC SMA OUT from the Oscilloscope ...

Page 51: ...with Gain R24 R25 392 Function Block Diagram Figure 5 9 is the function block diagram of this demonstration The built in MIC is amplified approximately 392 times via two operational amplifiers The signal is then feed into the ADC of MAX 10 device for conversion This demonstration uses the timing from the audio codec TLV320AIC3254 via I2S protocol to sync the entire system The module SPI_CTL sets t...

Page 52: ...onstration Setup Please make sure Quartus II and USB Blaster II driver are installed on the host PC Connect the USB cable from the USB Blaster II port J8 to the host PC Plug in the 5V adapter to the MAX 10 Plus board and power it up Execute the demo batch file test bat from the directory adc_mic demo_batch The sound wave from the MIC can be observed on the LED and probed through DAC SMA OUT from t...

Page 53: ...er Manual 53 www terasic com May 31 2019 Figure 5 10 The Waveform of onboard MIC is Displayed on the Oscilloscope Its Sound is Played out from the Speaker Figure 5 11 LEDR0 7 Displays the Volume Level of onboard MIC ...

Page 54: ... demo project 6 1 Power Monitor The power monitor demo shows how to measure the power consumed through the onboard power monitor chip LTC2990 There are three LTC2990 to monitor the following power rails 3 3V VCCIO 2 5V Core 2 5V VCCIO 1 5V VCCIO 1 2V VCC The power monitor chip LTC2990 communicates with the FPGA via I2C protocol The I2C OpenCore IP is used in this demonstration for the MAX 10 devic...

Page 55: ...n be calculated by the following formula Power Consumption VCC x Current VCC x V1 V2 RSENSE Figure 6 2 Schematic of Current Sense Figure 6 3 shows the register content of LTC2990 The voltage difference V1 V2 measured are written into two registers MSB register 06h and LSB register 07h The most significant bit 7th bit of MSB register is the data_valid bit which indicates whether the current registe...

Page 56: ...owing equations are used to convert the register values to get the differential voltage Figure 6 3 Register of LTC2990 Figure 6 4 shows the control register of LTC2990 The control register must be configured properly to measure the voltage difference V1 V2 Bits b 2 0 should be set to 110 for measuring voltage difference V1 V2 and V3 V4 Bits 4 3 should be set to 00 for all measurements Figure 6 4 C...

Page 57: ...er Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse Demonstration Batch File Demo batch file folder Demonstrations power_monitor_nios demo_batch Batch file test bat FPGA configuration file power_monitor_nios sof Nios batch file test sh NIOS program nios_app elf Demonstration Setup Please follow the procedures below to set up the demo...

Page 58: ...e data format Developers can use a USB cable rather than a RS232 cable to enable the communication between the FPGA and the host computer In this demonstration we will show you how to control the LEDRs by sending a command on the computer putty terminal The command is sent and received through a USB cable to the FPGA Note that in FPGA the information was received and sent through a UART IP Figure ...

Page 59: ...e the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse Demonstration Batch File Demo Batch File Folder uart_usb demo_batch The demo batch file includes following files Batch Files uart_usb bat uart_usb sh FPGA Configure File uart_usb sof Nios II Program uart_usb elf Demonstration Setup Please follow the procedu...

Page 60: ...e USB Serial Port to update the driver software The driver file can be downloaded from the following website http www ftdichip com Drivers VCP htm Open the Device Manager to ensure which common port is assigned to the UART to USB port as shown in Figure 6 9 The common number 9 COM9 is assigned on this computer Figure 6 9 Check the Assigned Com Port Number On PC Open the putty software type in the ...

Page 61: ... and putty terminal is shown in Figure 6 11 Figure 6 11 Running Result of Uart_USB Demo In the putty terminal type any character to change the LED state Type a digital number to toggle the LEDR 9 0 state and type a A or n N to turn on off all LEDR 6 3 SD Card Audio Demonstration Many commercial media audio players use a large external storage device such as an SD Card or CF card to store music or ...

Page 62: ...ck provided from the board The PLL generates a 100MHz clock for Nios II processor and the other controllers The audio chip is controlled by the Audio Controller which is a user defined SOPC component The internal PLL in the CODEC chip can generate the clock rate according to the sample rate of the music A mater clock should be supplied for the CODEC The mater clock rate in this demonstration is 19...

Page 63: ...system for reading wave files that are stored in the SD Card In this block only read function is implemented The WAVE Lib block implements WAVE file decoding function for extracting audio data from wave files The I2C block implements I2C protocol for configuring audio chip The Audio block implements audio FIFO checking function and audio signal sending receiving function The key and switch block a...

Page 64: ...Nios II Eclipse project workspace sdcard_audio software Nios II Project Compilation Before you attempt to compile the reference design under Nios II Eclipse make sure the project is cleaned first by clicking Clean from the Project menu of Nios II Eclipse Demonstration Batch File Demo Batch File Folder sdcard_audio demo_batch The demo batch file includes following files Batch Files test bat test sh...

Page 65: ...te how to perform DDR3 memory access in Qsys We describe how the Altera s DDR3 SDRAM Controller with UniPHY IP is used to access a DDR3 SDRAM and how the Nios II processor is used to read and write the SDRAM for hardware verification The DDR3 SDRAM controller handles the complex aspects of using DDR3 SDRAM by initializing the memory devices managing SDRAM banks and keeping the devices refreshed at...

Page 66: ...completed the result is displayed in the JTAG Terminal Altera DDR3 SDRAM Controller with UniPHY To use Altera DDR3 controller you need to perform 4 major steps Create correct pin assignments for DDR3 Set up correct parameters in DDR3 controller dialog Perform Analysis and Synthesis by clicking Quartus menu Process Start Start Analysis Synthesis Run the TCL files generated by DDR3 IP by clicking Qu...

Page 67: ... II and Nios II are installed on your PC Power on the MAX 10 Plus board Use an USB cable to connect PC and the MAX 10 Plus board J8 and install USB Blaster driver if necessary Execute the demo batch file ddr3_nios bat for USB Blaster II under the batch file folder ddr3_nios demo_batch After Nios II program is downloaded and executed successfully a prompt message will be displayed in Nios2 terminal...

Page 68: ...te designed to provide an optimal solution for network related applications accompanying Nios II Also to understand how this demo works we assume that you already have a basic knowledge of TCP IP protocols As indicated in the block diagram in Figure 6 18 the Nios II processor is used to communicate with the Client via 88E1111 RGMII MII interface Ethernet Device Figure 6 18 Block Diagram We will no...

Page 69: ...O Module should be included as it is used to generate a 2 5MHz MDC clock for the PHY chip from the controller s source clock here a 100MHz clock source is expected to divide the MAC control register interface clock to produce the MDC clock output on the MDIO interface The MAC control register interface clock frequency is 100MHz and the desired MDC clock frequency is 2 5MHz so a host clock divisor ...

Page 70: ...asic com May 31 2019 Figure 6 20 MAC Options Configuration Once the Triple Speed Ethernet IP configuration has been set and necessary hardware connections have been made as shown in Figure 6 21 click on generate Figure 6 21 Qsys Builder ...

Page 71: ...e Nios II processor and the necessary hardware to be implemented into the MAX 10 Plus board The software device drivers contain the necessary device drivers needed for the Ethernet and other hardware components to work The HAL API block provides the interface for the software device drivers while the Micro C OS II provides communication services to the NicheStack and the Socket Server The NicheSta...

Page 72: ...heir transmission parameters speed and duplex mode After the auto negotiation process has been finished the link will be established Next the Socket Server program will prepare the transmitting and receiving path for the link If the path is created successfully it will call the get_ip_addr function to set up the IP address for the network interface After the IP address is successfully distributed ...

Page 73: ...ures below to set up the demonstration Please make sure both Quartus II and USB Blaster II driver are installed on the host PC Connect the USB cable from the USB Blaster II port J8 on the MAX 10 Plus board to the host PC Power on the MAX 10 Plus board Execute the demo batch file socket_server bat under the folder Demonstrations socket_server demo_batch then the IP address and port number are assig...

Page 74: ...pen_telnet bat file please try to set the Telnet Client feature as following screenshot From the Simple Socket Server Menu enter the commands in the telnet session Entering a number from zero through seven followed by a return causes the corresponding LEDRs D0 D7 to toggle on or off on the MAX 10 Plus board as shown below in Figure 6 26 ...

Page 75: ...ic acceleration of gravity In our Nios II software we compute the change of angle in the x axis and y axis and show the angle data on the Nios II Console The value of light sensor will change as the brightness changes around the light sensor Figure 6 27 shows the hardware system block diagram of this demonstration The system is clocked by an external 50MHz Oscillator Through the internal PLL modul...

Page 76: ...dures below to set up the demonstration Load the bit stream into the FPGA on the MAX 10 Plus board Run the Nios II Software under the workspace gsensor_lightsensor software Note After the Nios II program is downloaded and executed successfully a prompt message will be displayed in Nios2 terminal its ADXL345 s ID e5 Tilt the MAX 10 Plus to all directions and you will find that the angle of the g se...

Page 77: ...ration and display results on the Nios II console Figure 6 29 Block Diagram of Humidity and Temperature Sensor This demonstration shows basic function of HDC1000 and temperature and humidity reading in different acquisition modes HDC1000 can perform measurements of both humidity and temperature or either humidity only or temperature only The measurement resolution can be set to 8 11 or 14 bits for...

Page 78: ...ions Please follow the procedures below to set up the demonstration Make sure Quartus II and USB Blaster II driver are installed on your PC Connect the USB cable to the USB Blaster II connector J8 on the MAX 10 Plus board and host PC Power on the MAX 10 Plus board Execute the demo batch file humidity_temperature bat under the batch file folder humidity_temperature demo_batch NIOS terminal and will...

Page 79: ...al Configuration The internal configuration scheme for all MAX 10 devices except for 10M02 device consists of the following mode Dual Compressed Images configuration image is stored as image0 and image1 in the configuration flash memory CFM Single Compressed Image Single Compressed Image with Memory Initialization Single Uncompressed Image Single Uncompressed Image with Memory Initialization In du...

Page 80: ... errors is as follows 1 After powering up the device samples the BOOT_SEL pin to determine which application configuration image to boot The BOOT_SEL pin setting can be overwritten by the input register of the remote system upgrade circuitry for the subsequent reconfiguration 2 If an error occurs the remote system upgrade feature reverts by loading the other application configuration image The fol...

Page 81: ... feature skip this section Two main steps are necessary for a project support dual configuration mode Add dual configuration IP Modify Configuration Mode in device setting A Dual Configuration IP should be added in an original project so that the pof file can be programmed into CFM through it Open Quartus project and choose Tools Qsys to open Qsys system wizard Create a new system and add the dual...

Page 82: ...e and Pin Options and choose Dual Compressed Images in configuration table as shown in Figure 7 5 Then compile the project to generate the sof file Figure 7 5 Set Dual Configuration Modes These procedures should be implemented in both projects for dual boot The next step is to convert the two sof files into a pof file for programming the MAX10 FPGA Open the convert programming Files tool in Quartu...

Page 83: ... press the Add Sof Page button and add a sof for image1 as shown in Figure 7 7 Click generate button to generate the object file dual_boot pof Figure 7 7 Add Sof Files The final step is to download the pof into MAX10 FPGA Open the programmer tool and add the dual_boot pof as shown in Figure 7 8 Click Start button to program the device when the hardware is set OK Figure 7 8 Download the pof ...

Page 84: ...emory for the MAX10 FPGA auto boot after power cycling The onchip flash memory in the FPGA provides the possibility to boot the software for the Nios II processor The demonstration my_first_niosII is designed for Nios II processor loading software after the FPGA configuration complete The section describes the detailed steps of the design An onchip flash controller ip should be added into the Qsys...

Page 85: ...lipse as shown in Figure 7 11 Figure 7 11 Make Target Setting After clicking build button a onchip_flash hex file will be generated in the path software software_project mem_init Open the convert programming file window in Quartus II and set the window as shown in Figure 7 12 Figure 7 12 Convert File Window Setting Click the Options Boot info button Choose the UFM source as the load memory file an...

Page 86: ...d Hex Data Window In the Input files to convert table choose the sof and generate the pof Open the programmer tool and add the pof generated above to download into the onchip flash Power cycle the board the Nios II software will be running after the image has been loaded ...

Page 87: ...MAX 10 Plus User Manual 87 www terasic com May 31 2019 Chapter 8 Appendix 8 1 Revision History Version Change Log V1 0 Initial Version 8 2 Copyright Statement Copyright Terasic Inc All rights reserved ...

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