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Chapter 6
NIOS-II Based Example Codes
This chapter provides a number of NIOS-II bases example codes designed for the starter board.
These examples provide demonstrations of the major features which connected to FPGA interface
on the board, such as audio, video, uart to usb, sdcard, sram, lpddr2 adn HDMI. All of the
associated files can be found in the
Demonstrations
folder on the System CD.
6
6
.
.
1
1
S
S
R
R
A
A
M
M
This demonstration presents a memory test function of
SRAM
on the
C5G
board. The memory size of
the
SRAM
is
512K
B.
System Block Diagram
s
hows the system block diagram of this demonstration. The system requires a
100
MHz
clock provided from the board. In the Qsys, Nios II and the On-Chip Memory are designed running
with the 100MHz clock, and the Nios II program is running in the on-chip memory.
