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Table 3-4
User LEDs Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Cyclone V GX
Pin Number
LEDR0
LEDR0
Driving a logic 1 on the I/O port turns the LED
ON.
Driving a logic 0 on the I/O port turns the LED
OFF.
2.5-V
PIN_F7
LEDR1
LEDR1
2.5-V
PIN_F6
LEDR2
LEDR2
2.5-V
PIN_G6
LEDR3
LEDR3
2.5-V
PIN_G7
LEDR4
LEDR4
2.5-V
PIN_J8
LEDR5
LEDR5
2.5-V
PIN_J7
LEDR6
LEDR6
2.5-V
PIN_K10
LEDR7
LEDR7
2.5-V
PIN_K8
LEDR8
LEDR8
2.5-V
PIN_H7
LEDR9
LEDR9
2.5-V
PIN_J10
LEDG0
LEDG0
2.5-V
PIN_L7
LEDG1
LEDG1
2.5-V
PIN_K6
LEDG2
LEDG2
2.5-V
PIN_D8
LEDG3
LEDG3
2.5-V
PIN_E9
LEDG4
LEDG4
2.5-V
PIN_A5
LEDG5
LEDG5
2.5-V
PIN_B6
LEDG6
LEDG6
2.5-V
PIN_H8
LEDG7
LEDG7
2.5-V
PIN_H9
User-Defined 7-Segment Displays
The FPGA board has four 7-segment displays. As indicated in the schematic in
, the
seven segments (common anode) are connected to pins on Cyclone V GX FPGA. Applying a low
logic level to a segment will light it up and applying a high logic level turns it off.
Please note that two 7-segment displays, HEX2 and HEX3, share bus with the GPIO. When using
HEX2 and HEX3, you need to switch the Dip Switch S1/S2 which is located on the back of the
board to the "ON" position before FPGA can control corresponding 7-segment displays.
Each segment in a display is identified by an index listed from 0 to 6 with the positions given in
. In addition, the decimal has no function at all.
shows the mapping of the
FPGA pin assignments to the 7-segment displays.
