Terasic Altera Cyclone V GX Starter Kit, User Manual

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DDR2LP_DM0 Data Write Mask (byte enables) 1.2-V HSUL PIN_AF11
DDR2LP_DM1 Data Write Mask (byte enables) 1.2-V HSUL PIN_AE18
DDR2LP_DM2 Data Write Mask (byte enables) 1.2-V HSUL PIN_AE20
DDR2LP_DM3 Data Write Mask (byte enables) 1.2-V HSUL PIN_AE24
DDR2LP_CK_p Differential Output Clock (positive) Differential 1.2-V HSUL PIN_N10
DDR2LP_CK_n Differential Output Clock (negative) Differential 1.2-V HSUL PIN_P10
DDR2LP_CKE0 Clock Enable 0 1.2-V HSUL PIN_AF14
DDR2LP_CKE1 Clock Enable 1 (Not use) 1.2-V HSUL PIN_AE13
DDR2LP_CS_n0 Chip Select 0 1.2-V HSUL PIN_R11
DDR2LP_CS_n1 Chip Select 1 (Not use) 1.2-V HSUL PIN_T11
DDR2LP_OCT_RZQ ZQ calibration.
E
xternal resistance (240Ω ±1%)
1.2-V HSUL PIN_AE11
3 3 . . 7 7 M M i i c c r r o o S S D D - - C C a a r r d d
The development board supports Micro SD card interface using x4 data lines. Figure 3-18 shows
the related signals connections between the SD Card and Cyclone V GX FPGA and Figure 3-19
shows micro SD card plug-in position.
Finally, Table 3-12 lists all the associated pins
Figure 3-18 Connection between the SD Card Socket and Cyclone V GX FPGA