33
HEX0
HEX0_D1
Seven Segment Digit 0[1]
2.5-V
PIN_V18
HEX0
HEX0_D2
Seven Segment Digit 0[2]
2.5-V
PIN_V17
HEX0
HEX0_D3
Seven Segment Digit 0[3]
2.5-V
PIN_W18
HEX0
HEX0_D4
Seven Segment Digit 0[4]
2.5-V
PIN_Y20
HEX0
HEX0_D5
Seven Segment Digit 0[5]
2.5-V
PIN_Y19
HEX0
HEX0_D6
Seven Segment Digit 0[6]
2.5-V
PIN_Y18
HEX1
HEX0_D0
Seven Segment Digit 1[0]
2.5-V
PIN_AA18
HEX1
HEX0_D1
Seven Segment Digit 1[1]
2.5-V
PIN_AD26
HEX1
HEX0_D2
Seven Segment Digit 1[2]
2.5-V
PIN_AB19
HEX1
HEX0_D3
Seven Segment Digit 1[3]
2.5-V
PIN_AE26
HEX1
HEX0_D4
Seven Segment Digit 1[4]
2.5-V
PIN_AE25
HEX1
HEX0_D5
Seven Segment Digit 1[5]
2.5-V
PIN_AC19
HEX1
HEX0_D6
Seven Segment Digit 1[6]
2.5-V
PIN_AF24
HEX2
HEX0_D0
Seven Segment Digit 2[0], Share GPIO22
3.3-V
PIN_AD7
HEX2
HEX0_D1
Seven Segment Digit 2[1] , Share GPIO23
3.3-V
PIN_AD6
HEX2
HEX0_D2
Seven Segment Digit 2[2] , Share GPIO24
3.3-V
PIN_U20
HEX2
HEX0_D3
Seven Segment Digit 2[3] , Share GPIO25
3.3-V
PIN_V22
HEX2
HEX0_D4
Seven Segment Digit 2[4] , Share GPIO26
3.3-V
PIN_V20
HEX2
HEX0_D5
Seven Segment Digit 2[5] , Share GPIO27
3.3-V
PIN_W21
HEX2
HEX0_D6
Seven Segment Digit 2[6] , Share GPIO28
3.3-V
PIN_W20
HEX3
HEX0_D0
Seven Segment Digit 3[0] , Share GPIO29
3.3-V
PIN_Y24
HEX3
HEX0_D1
Seven Segment Digit 3[1] , Share GPIO30
3.3-V
PIN_Y23
HEX3
HEX0_D2
Seven Segment Digit 3[2] , Share GPIO31
3.3-V
PIN_AA23
HEX3
HEX0_D3
Seven Segment Digit 3[3] , Share GPIO32
3.3-V
PIN_AA22
HEX3
HEX0_D4
Seven Segment Digit 3[4] , Share GPIO33
3.3-V
PIN_AC24
HEX3
HEX0_D5
Seven Segment Digit 3[5] , Share GPIO34
3.3-V
PIN_AC23
HEX3
HEX0_D6
Seven Segment Digit 3[6] , Share GPIO35
3.3-V
PIN_AC22
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The development board includes one 50MHz and one programmable Clock Generator
shows the
default frequencies of on-board external clocks going to the Cyclone V GX FPGA.
