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Table 3-2 Push-button Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Cyclone V GX
Pin Number
KEY0
KEY0
High Logic Level when the button is not
pressed. The four push buttons (KEY0,
KEY1, KEY2, and KEY3) go through the
debounce circuit.
1.2-V
PIN_P11
KEY1
KEY1
1.2-V
PIN_P12
KEY2
KEY2
1.2-V
PIN_Y15
KEN3
KEN3
1.2-V
PIN_Y16
KEY4
CPU_RESET_n
High Logic Level when the button is not
pressed.
3.3-V
PIN_AB24
User-Defined Slide Switch
There are ten slide switches connected to FPGA on the board (See
). These switches are
not debounced, and are assumed for use as level-sensitive data inputs to a circuit. Each switch is
connected directly to a pin on the Cyclone V GX FPGA. When the switch is in the DOWN position
(closest to the edge of the board), it provides a low logic level to the FPGA, and when the switch is
in the UP position it provides a high logic level.
lists the signal names and their corresponding Cyclone V GX device pin numbers.
Figure 3-9 Connections between the slide switches and Cyclone V GX FPGA
