44
Figure 3-21 Connections between FPGA and Audio CODEC
Table 3-14
Audio CODEC
Pin Assignments, Schematic Signal Names, and Functions
Schematic
Signal Name
Description
I/O Standard
Cyclone V GX
Pin Number
AUD_ADCLRCK
Audio CODEC ADC LR Clock
2.5-V
PIN_C7
AUD_ADCDAT
Audio CODEC ADC Data
2.5-V
PIN_D7
AUD_DACLRCK
Audio CODEC DAC LR Clock
2.5-V
PIN_G10
AUD_DACDAT
Audio CODEC DAC Data
2.5-V
PIN_H10
AUD_XCK
Audio CODEC Chip Clock
2.5-V
PIN_D6
AUD_BCLK
Audio CODEC Bit-Stream Clock
2.5-V
PIN_E6
I2C_SCL
I2C Clock
2.5-V
PIN_B7
I2C_SDA
I2C Data
2.5-V
PIN_G11
3
3
.
.
1
1
0
0
H
H
S
S
M
M
C
C
:
:
H
H
i
i
g
g
h
h
-
-
S
S
p
p
e
e
e
e
d
d
M
M
e
e
z
z
z
z
a
a
n
n
i
i
n
n
e
e
C
C
a
a
r
r
d
d
The FPGA development board contains one HSMC connector. The HSMC connector provides a
mechanism to extend the peripheral-set of an FPGA host board by means of add-on cards, which
can address today’s high speed signaling requirement as well as low-speed device interface support.
The HSMC interfaces support JTAG, clock outputs and inputs, high-speed serial I/O (transceivers),
and single-ended or differential signaling.
The HSMC interface connected to the Cyclone V GX device is a female HSMC connector having a
total of 172pins, including 121 signal pins (120 signal pins +1 PSNTn pin), 39 power pins, and 12
ground pins. The HSMC connector is based on the SAMTEC 0.5 mm pitch, surface-mount QSH
family of high-speed, board-to-board connectors. The Cyclone V GX device pr12 V DC
and +3.3 V DC power to the mezzanine card through the HSMC connector.
indicates the
