Terasic Altera Cyclone V GX Starter Kit, User Manual

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Figure 3-13 Clock circuit of the FPGA Board
The programming Clock Generator is a highly flexible and configurable clock generator/buffer. The
is to provide special and high quality clock signals for high-speed transceivers. The clock generator
is controlled by the FPGA through the I2C serial interface. The user can modify the frequency
between 0.16 MHz to 200 MHz.
Table 3-6 lists the clock source, signal names, default frequency and their corresponding Cyclone V
GX device pin numbers. Table 3-7 lists the programmable Clock Generator control pins, signal
names, I/O standard and their corresponding Cyclone V GX device pin numbers.
Table 3-6 Clock Source, Signal Name, Default Frequency, Pin Assignments and Functions
Source
Schematic
Signal Name
Default
Frequency
I/O Standard
Cyclone V GX
Pin Number
Application
X2 CLOCK_50_B3B 50.0 MHz 1.2-V PIN_T13
U20 CLOCK_125_p 125.0 MHz LVDS PIN_U12
U20 CLOCK_125_n 125.0 MHz LVDS PIN_V12
X2
CLOCK_50_B5B 50.0 MHz 3.3-V PIN_R20
CLOCK_50_B6A 50.0 MHz 3.3-V PIN_N20
U20 CLOCK_50_B7A 50.0 MHz 2.5-V PIN_H12
U20 CLOCK_50_B3A 50.0 MHz 2.5-V PIN_M10
U20 REFCLK_p0 125.0 MHz 1.5-V PCML PIN_V6
U20 REFCLK_n0 125.0 MHz 1.5-V PCML PIN_W6
U20 REFCLK_p1 156.25 MHz 1.5-V PCML PIN_N7
U20 REFCLK_n1 156.25 MHz 1.5-V PCML PIN_P6