65
Restore Factory Configuration
•
Ensure that power is applied to the C5G board.
•
Connect the supplied USB cable to the USB Blaster port on the C5G board.
•
Configure the JTAG programming circuit by setting the RUN/PROG slide switch (SW11) to the
PROG position.
•
Execute the demo batch file “ pof_C5G_Default
.bat
” for USB-Blaster under the batch file
folder,C5G_Default/demo_batch.
•
Once the programming operation is finished, set the RUN/PROG slide switch back to the RUN
position and then reset the board by turning the power switch off and back on; this action causes
the new configuration data in the EPCQ256 device to be loaded into the FPGA chip.
5
5
.
.
2
2
L
L
P
P
D
D
D
D
R
R
2
2
S
S
D
D
R
R
A
A
M
M
R
R
T
T
L
L
T
T
e
e
s
s
t
t
This demonstration presents a memory test function on the bank of
LP
DDR
2
-SDRAM on the
C5G
board. The memory size of the
LP
DDR
2
SDRAM bank is
512M
B.
Function Block Diagram
shows the function block diagram of this demonstration. The controller uses
125
MHz
as a reference clock, generates one 330 MHz clock as memory clock, and generates one
full
-rate
system clock 330MHz for the controller itself.
Figure 5-1 Block Diagram of the LPDDR2 SDRAM (
512M
B
) Demonstration
RW_test modules read and write the entire memory space of the LPDDR2 through the Avalon
interface of the controller. In this project, the Avalon bus read/write test module will first write the
entire memory and then compare the read back data with the regenerated data (the same sequence as
the write data). KEY0 will trigger test control signals for the LPDDR2, and the LEDs will indicate
the test results according to
