Terasic Altera Cyclone V GX Starter Kit, User Manual

Page: 39 / 95

38
available on the manufacturer’s website, or under the Datasheets\LPDDR2 folder on the Kit System
CD.
Figure 3-17 shows the related schematics and Table 3-11 lists the LPDDR2 pin assignments,
signal names, and functions.
Figure 3-16 Connections between the Cyclone V GX FPGA and LPDDR2 Chip
Figure 3-17 LPDDR2 and Cyclone V GX FPGA
Table 3-11 LPDDR2 Memory Pin Assignments, Schematic Signal Names, and Functions
Schematic
Signal Name
Description I/O Standard
Cyclone V GX
Pin Number
DDR2LP_CA0 Command/address bus 1.2-V HSUL PIN_AE6
DDR2LP_CA1 Command/address bus 1.2-V HSUL PIN_AF6
DDR2LP_CA2 Command/address bus 1.2-V HSUL PIN_AF7
DDR2LP_CA3 Command/address bus 1.2-V HSUL PIN_AF8
DDR2LP_CA4 Command/address bus 1.2-V HSUL PIN_U10