37
SRAM_A5
Address bus
3.3-V
PIN_C25
SRAM_A6
Address bus
3.3-V
PIN_J20
SRAM_A7
Address bus
3.3-V
PIN_J21
SRAM_A8
Address bus
3.3-V
PIN_D22
SRAM_A9
Address bus
3.3-V
PIN_E23
SRAM_A10
Address bus
3.3-V
PIN_G20
SRAM_A11
Address bus
3.3-V
PIN_F21
SRAM_A12
Address bus
3.3-V
PIN_E21
SRAM_A13
Address bus
3.3-V
PIN_F22
SRAM_A14
Address bus
3.3-V
PIN_J25
SRAM_A15
Address bus
3.3-V
PIN_J26
SRAM_A16
Address bus
3.3-V
PIN_N24
SRAM_A17
Address bus
3.3-V
PIN_M24
SRAM_D0
Data bus
3.3-V
PIN_E24
SRAM_D1
Data bus
3.3-V
PIN_E25
SRAM_D2
Data bus
3.3-V
PIN_K24
SRAM_D3
Data bus
3.3-V
PIN_K23
SRAM_D4
Data bus
3.3-V
PIN_F24
SRAM_D5
Data bus
3.3-V
PIN_G24
SRAM_D6
Data bus
3.3-V
PIN_L23
SRAM_D7
Data bus
3.3-V
PIN_L24
SRAM_D8
Data bus
3.3-V
PIN_H23
SRAM_D9
Data bus
3.3-V
PIN_H24
SRAM_D10
Data bus
3.3-V
PIN_H22
SRAM_D11
Data bus
3.3-V
PIN_J23
SRAM_D12
Data bus
3.3-V
PIN_F23
SRAM_D13
Data bus
3.3-V
PIN_G22
SRAM_D14
Data bus
3.3-V
PIN_L22
SRAM_D15
Data bus
3.3-V
PIN_K21
SRAM_CE_n
Chip Enable, active Low
3.3-V
PIN_N23
SRAM_OE_n
Output Enable, active Low
3.3-V
PIN_M22
SRAM_WE_n
Write Enable, active Low
3.3-V
PIN_G25
SRAM_LB_n
Lower-Byte Control, D0~D7, active Low
3.3-V
PIN_H25
SRAM_UB_n
Upper-Byte Control, D8~D15, active Low
3.3-V
PIN_M25
3
3
.
.
6
6
L
L
P
P
D
D
D
D
R
R
2
2
M
M
e
e
m
m
o
o
r
r
y
y
The development board has one 4Gb Mobile Low-Power DDR2 SDRAM (LPDDR2) which is a high-speed
CMOS, dynamic random-access memory containing 4,294,967,296-bits shown in
For detailed information on how to use the LPDDR2, please refer to the datasheet, which is
