76
Pixel Data [23:0]
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R[7:0]
G[7:0]
B[7:0]
Figure 6-8 Build-in Display Modes of the HDMI TX Demonstration
A set of display modes are implemented for presenting the generated video patterns. The module
“Video Source Selector” controls the selection of current video timing among build-in display
modes listed in
. The module "Mode Control" allows users to switch current display mode
alternatively via the KEY1 push button.
Table 6-1 Build-in Display Modes of the HDMI TX Demonstration
Pattern ID
Video Format
PCLK (MHZ)
0
640x480@60P
25
1
720x480@60P
27
2
1024x768@60P
65
3
1280x1024@60P
108
4
1920x1080@60P
148.5
5
1600x1200@60P
162
In the VPG module, the Altera IP “PLL Reconfig” is used to set up pixel frequency of
corresponding mode to the Altera IP “PLL.” The RECONFIG data for each clock frequency is
originated from the “PLL Controller.” The source of the VPG module is located at the
“
C5G_HDMI_VPG\vpg_source
” folder.
