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Figure 2-11 HSMC loopback verification test performed under Control Panel
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The C5G Control Panel is based on a Nios II Qsys system instantiated in the Cyclone V GX FPGA
with software running on the on-chip memory. The software part is implemented in C code; the
hardware part is implemented in Verilog HDL code with Qsys builder. The source code is not
available on the C5G System CD.
To run the Control Panel, users should make the configuration according to Section 3.1.
depicts the structure of the Control Panel. Each input/output device is controlled by the Nios II
Processor instantiated in the FPGA chip. The communication with the PC is done via the USB
Blaster link. The Nios II interprets the commands sent from the PC and performs the corresponding
actions.
