46
There are three banks in this connector.
shows the bank arrangement of signals with
respect to the SAMTEC connector.
lists the mapping of the FPGA pin assignments to
the HSMC connectors.
Figure 3-23 HSMC Signal Bank Diagram
Table 3-16 Power Supply of the HSMC
Supplied Voltage
Max. Current Limit
12V
1A
3.3V
1.5A
Table 3-17 Pin Assignments for HSMC connector
Schematic
Signal Name
Description
I/O Standard
Cyclone V GX
Pin Number
HSMC_CLKIN0
Dedicated clock input
2.5-V
PIN_N9
HSMC_CLKIN_n1
LVDS RX or CMOS I/O or
differential clock input
2.5-V or LVDS
PIN_G14
HSMC_CLKIN_n2
LVDS RX or CMOS I/O or
2.5-V or LVDS
PIN_K9