TeleChips TCC720, User Manual

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TCC720
USB CONTROLLER
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
8 - 10
EP0 CSR Register (EP0CSR) 0x80000544
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
CLSE CLOR ISST CEND DEND STAL IRDY ORDY
*) EP0 CSR register can access by writing “0” to UBIDX register, and use same address as INCSR1.
CLSE
[7]
Type Clear Setup End Bit
1 W The SEND bit is cleared
CLOR
[6]
Type Clear Output Packet Ready Bit
1 W The ORDY bit is cleared
ISST
[5]
Type Issue STALL Handshake
1 R/W Start issuing a STALL Handshake. At the same time, it clears
ORDY bit if it decodes an invalid token
0 W End the STALL condition
CEND
[4]
Type Control Setup End
1 R Indicates that the control transfer ends before DEND bit is set
0 R Indicates that the CLSE is written by “1”.
At the same time,
the USB flushes the FIFO, and invalidates
access to the FIFO. That is, when the access to the FIFO is
invalidated, this bit is cleared.
DEND
[3]
Type Data End
1 R Indicates that the one of the following conditions matched.
-
after loading the last packet of data into the FIFO.
(at the same time IRDY is set)
-
while it clears ORDY after unloading the last packet of data.
-
for a zero length data phase
(at the same time, it clears ORDY and sets IRDY)
STAL
[2]
Type IN Packet Ready
1 R Indicates that a control transaction is ended due to a protocol
violation