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TCC720

TIMER / COUNTER

32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002

Preliminary Spec 0.51

5 - 2

the TREF, TCNT register has 20bit resolution. It can be used for generation of a long time

period.

5.2 Register Description

Timer/Counter Register Map (Base Address = 0x80000200)

Name

Address

Type

Reset

Description

TCFG0 0x0000 R/W 0x00 Timer/Counter 0 Configuration Register

TCNT0 0x0004 R/W 0x0000 Timer/Counter 0 Counter Register

TREF0

0x0008

R/W

0xFFFF

Timer/Counter 0 Reference Register

TMREF0 0x000C R/W 0x0000 Timer/Counter 0 Middle Reference Register

TCFG1 0x0010 R/W 0x00 Timer/Counter 1 Configuration Register

TCNT1 0x0014 R/W 0x0000 Timer/Counter 1 Counter Register

TREF1

0x0018

R/W

0xFFFF

Timer/Counter 1 Reference Register

TMREF1 0x001C R/W 0x0000 Timer/Counter 1 Middle Reference Register

TCFG2 0x0020 R/W 0x00 Timer/Counter 2 Configuration Register

TCNT2 0x0024 R/W 0x0000 Timer/Counter 2 Counter Register

TREF2

0x0028

R/W

0xFFFF

Timer/Counter 2 Reference Register

TMREF2 0x002C R/W 0x0000 Timer/Counter 2 Middle Reference Register

TCFG3 0x0030 R/W 0x00 Timer/Counter 3 Configuration Register

TCNT3 0x0034 R/W 0x0000 Timer/Counter 3 Counter Register

TREF3

0x0038

R/W

0xFFFF

Timer/Counter 3 Reference Register

TMREF3 0x003C R/W 0x0000 Timer/Counter 3 Middle Reference Register

TCFG4 0x0040 R/W 0x00 Timer/Counter 4 Configuration Register

TCNT4 0x0044 R/W 0x00000 Timer/Counter 4 Counter Register

TREF4

0x0048

R/W

0xFFFFF

Timer/Counter 4 Reference Register

TCFG5 0x0050 R/W 0x00 Timer/Counter 5 Configuration Register

TCNT5 0x0054 R/W 0x00000 Timer/Counter 5 Counter Register

TREF5

0x0058

R/W

0xFFFFF

Timer/Counter 5 Reference Register

TIREQ 0x0060 R/W 0x0000 Timer/Counter n Interrupt Request Register

TWDCFG 0x0070 R/W 0x0000 Watchdog

Timer Configuration Register

TWDCLR

0x0074

Watchdog Timer Clear Register

Summary of Contents for TCC720

Page 1: ...USER S MANUAL TCC720 32 bit RISC Microprocessor For Digital Media Player Preliminary Rev 0 51...

Page 2: ...TER 6 GPIO 7 CLOCK GENERATOR 8 USB Universal Serial Bus CONTROLLER 9 UART IrDA 10 GSIO General Purpose Serial Input Output 11 MISCELLANEOUS PERIPHERALS 11 1 ADC 11 2 CODEC 12 DMA CONTROLLER 13 MEMORY...

Page 3: ...CHAPTER 1 INTRODUCTION...

Page 4: ...or other types of audio voice compression decompression standards by software based architecture The on chip USB controller enables the data transmission between a personal computer and storage of de...

Page 5: ...USB device 4 external interrupts 9 internal interrupts 4 timer counters 2 timers USB1 1 device Full speed UART IrDA for serial Host I F GPIO GSIO I2S interface for internal and external audio CODEC I2...

Page 6: ...A16 ND_ALE SD_nRAS XA15 SD_nCAS XA14 SD_BA1 XA13 SD_BA0 XA 12 0 XD 15 0 nOE nWE nCS 3 0 GPIO_B 5 2 SD_nCS GPIO_B1 SD_CKE GPIO_B0 SD_CLK ND_nWE GPIO_B7 IDE_nCS1 GPIO_B9 TDI TMS TCK nTRST TDO XIN XOUT X...

Page 7: ...A 17 XA 19 18 40 39 O XA 19 18 for static memory Bus Width configuration XA 21 20 DQM 0 1 43 42 O XA 21 20 Data I O mask XD 15 9 XD 8 4 XD 3 0 XD 15 9 XD 8 4 XD 3 0 15 9 6 2 128 125 I O Data bus for e...

Page 8: ...0 SCK_0 CDIF 2 0 CDAI CLRCK CBCLK 107 105 I O GPIO_A 3 1 General purpose serial I O 0 CD interface signals GPIO_A 0 GSIO0 0 SDO_0 104 I O GPIO_A 0 General purpose serial out 0 GPIO_B 29 28 54 53 I O G...

Page 9: ...ADC left channel input of internal audio CODEC RCH_IN RCH_IN 91 I ADC right channel input of internal audio CODEC MIC_IN MIC_IN 92 I Mic input of internal audio CODEC LCH_OUT LCH_OUT 93 O DAC left ch...

Page 10: ...ode Control Signal Shared Signal NUM Type Description MODE1 98 I Mode Setting Input 1 nRESET 72 I System Reset Power Signal NUM Type Description VDD3 112 76 64 33 16 PWR Digital Power for I O 3 3V VDD...

Page 11: ...CAS XA16 nRAS ALE XA17 CLE XA18 XA19 VDDI XA20 DQM1 XA21 DQM0 SD_CLK GPO VSSIO SD_nCS GPIO_B1 nCS0 nOE0 GPIO_B2 nCS1 nOE1 GPIO_B3 nCS2 nOE2 GPIO_B4 nCS3 nOE3 GPIO_B5 USB_DP GPIO_B26 USB_DN GPIO_B27 GP...

Page 12: ...CHAPTER 2 ADDRESS REGISTER MAP...

Page 13: ...x4FFFFFFF Initial area for chip select 0 Initial configuration is for SRAM 0x50000000 0x5FFFFFFF Initial area for chip select 1 Initial configuration is for IDE type device 0x60000000 0x6FFFFFFF Initi...

Page 14: ...d for preventing illegal accessing Refer to corresponding sections for detail information of each peripheral Table 2 2 Address Allocation for Internal Peripherals Base Address 0x80000000 Offset Addres...

Page 15: ...tal Audio Right Output Register 1 DAMR 0x20 R W 0x0000 Digital Audio Mode Register DAVC 0x24 R W 0x0000 Digital Audio Volume Control Register CDDI_0 0x80 R CD Digital Audio Input Register 0 CDDI_1 0x8...

Page 16: ...T2 0x0024 R W 0x0000 Timer Counter 2 Counter Register TREF2 0x0028 R W 0xFFFF Timer Counter 2 Reference Register TMREF2 0x002C R W 0x0000 Timer Counter 2 Middle Reference Register TCFG3 0x0030 R W 0x0...

Page 17: ...EL_B 0x18 R W 0x3C0000BF GPIO_B Function Select Register GTSEL_B 0x1C R W 0x00000000 GPIO_B Function Select Register 2 Clock Generator Register Map Base Address 0x80000400 Name Address Type Reset Desc...

Page 18: ...In Interrupt Enable Register UBOIEN 0x24 Out Interrupt Enable Register UBIEN 0x2C Interrupt Enable Register UBFRM1 0x30 Frame Number 1 Register UBFRM2 0x34 Frame Number 2 Register UBIDX 0x38 Index Reg...

Page 19: ...gister 1 IrDACFG2 0x18 R W 0x4da1 IrDA Configuration Register 2 GSIO Register Map Base Address 0x80000700 Name Address Type Reset Description GSDO0 0x00 R W GSIO0 Output Data Register GSDI0 0x04 R W G...

Page 20: ...ADR 0x10 R W Start Address of Destination Block DPARAM 0x14 0x18 R W Parameter of Destination Block C_DADR 0x1C R Current Address of Destination Block HCOUNT 0x20 R W 0x00000000 Initial and Current Ho...

Page 21: ...sh Register Map Base Address N 0x10000000 Name Address Type Reset Description CMD 0x00 R W Command Cycle Register LADDR 0x04 W Linear Address Cycle Register BADDR 0x08 W Block Address Cycle Register I...

Page 22: ...CHAPTER 3 DAI CDIF...

Page 23: ...ion the DCO function is very useful to generate a system clock Refer Chap 7 for detail information All three clocks are selectable as master or slave The DAI DAO are the serial data input output pins...

Page 24: ...Audio Right Input Register 0 DADI_L1 0x08 R Digital Audio Left Input Register 1 DADI_R1 0x0C R Digital Audio Right Input Register 1 DADO_L0 0x10 R W Digital Audio Left Output Register 0 DADO_R0 0x14...

Page 25: ...r disabled 1 DAI transmitter enabled RE 13 DAI Receiver Enable 0 DAI receiver disabled 1 DAI receiver enabled MD 12 DAI Bus Mode 0 DAI has IIS bus mode 1 DAI has MSB justified mode SM 11 DAI System Cl...

Page 26: ...fs 32fs FD 5 4 DAI Frame Clock Divider select 00 Div 32 32fs fs 01 Div 48 48fs fs 10 Div 64 64fs fs BP 3 DAI Bit Clock Polarity 0 Data is captured at positive edge of bit clock 1 Data is captured at n...

Page 27: ...Control Register DAVC 0x80000024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved VC 3 0 VC 3 0 DAI Volume control 0000 0dB 0001 6dB 0010 12dB 00...

Page 28: ...HT1 LEFT2 RIGHT2 LEFT3 RIGHT3 LEFT0 RIGHT0 LEFT1 RIGHT1 LEFT2 RIGHT2 LEFT3 RIGHT3 DADI DADO Input Buffer Pointer Output Buffer Pointer Input Buffer Output Buffer S2P IIS_SDI P2S IIS_SDO IIS_MCLK S M I...

Page 29: ...S B L S B M S B 15 3 2 1 16 LRCK BCLK DAI O MD 0 IIS mode BP 0 BCLK 32fs L S B Right Left 29 28 27 10 9 8 7 31 6 5 4 M S B M S B 30 3 2 1 32 LRCK BCLK DAI O 32 MD 1 MSB justified mode BP 0 BCLK 64fs...

Page 30: ...I_1 are the banked read only registers for access of data input buffer The data input buffer is composed of four 32 bit wide registers of which upper 16 bit is left channel data and lower is right cha...

Page 31: ...20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EN Reserved BS MD BP EN 7 CDIF Enable 0 CDIF disabled 1 CDIF enabled BS 3 2 CDIF Bit Clock select 00 64fs 01 32fs 10 48fs MD 1 I...

Page 32: ...Input Buffer Pointer Input Buffer S2P CDAI CBCLK CLRCK CDDI1 Figure 3 3 CDIF Block Diagram Right Left 22 21 20 19 10 9 8 7 24 6 5 4 M S B L S B M S B 23 3 2 1 16 CLRCK CBCLK CDAI MD 0 IIS mode BP 0 CB...

Page 33: ...CHAPTER 4 INTERRUPT CONTROLLER...

Page 34: ...l low detection can be set for external interrupt sources External interrupt sources can be reliably managed with noise filtering up to 100 400 us There are two types of interrupt in ARM940T IRQ type...

Page 35: ...8 R W 0x0000 Test Mode Register must be remained zero Interrupt Enable Register IEN 0x80000100 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MEN DMA LCD CDIF GS UB UT TC I2T I2R E3 E2 E1 E0 MEN 15 Master Enab...

Page 36: ...UT TC I2T I2R E3 E2 E1 E0 When each field is 1 the corresponding interrupt is considered as IRQ interrupt otherwise as FIQ interrupt External Interrupt Configuration Register ICFG 0x80000110 15 14 13...

Page 37: ...e filter delay has about 16us 1 Delay cell based filter is used The filter delay varies on the operating conditions like voltage temperature etc The nominal delay is about 120ns This type of filter mu...

Page 38: ...CHAPTER 5 TIMER COUNTER...

Page 39: ...be configured by setting TCLK frequency Refer to Clock generator block With the 12bit internal basic counter the timer counter can generate various intervals from micro seconds to seconds unit The fol...

Page 40: ...x0020 R W 0x00 Timer Counter 2 Configuration Register TCNT2 0x0024 R W 0x0000 Timer Counter 2 Counter Register TREF2 0x0028 R W 0xFFFF Timer Counter 2 Reference Register TMREF2 0x002C R W 0x0000 Timer...

Page 41: ...divider circuit It is driven by PCLK and this value determines the division factor of this circuit Division factor is 22k k 7 TCK is the external pin shared by external interrupt signal In TCC721 ther...

Page 42: ...at every pulse of selected clock source TCNTn can be set to any value by writing the value to this register In case of timer 4 and timer 5 it has 20bit Timer Counter n Counting Reference Register TREF...

Page 43: ...chdog Timer Interrupt Request Flag 1 Watchdog timer has generated its interrupt TIn Timer Counter n Interrupt Request Flag 1 Timer counter n has generated its interrupt if a timer n has reached its re...

Page 44: ...sion factor of this circuit Division factor is 22k k 7 Undefined Should not be used IEN 3 Interrupt Enable 1 Watchdog Timer Interrupt is initiated This field is valid only if RST field is set to 0 RST...

Page 45: ...CHAPTER 6 GPIO PORT...

Page 46: ...TSEL 0 2 GIOCON 1 0 1 Output of test or other block Figure 6 1 GPIO Block Diagram The I O mode can be set by the state of GIOCONn register If a bit of GIOCONn register is 1 the corresponding GPIO pin...

Page 47: ...he dedicated GPIO pins This option is controlled by the state of the GSELx register If a bit of these GSELx is 1 the corresponding GPIO pin is entered to other function mode so used by other periphera...

Page 48: ...O_A Data Register GIOCON_A 0x04 R W 0x00000000 GPIO_A Direction Control Register GSEL_A 0x08 R W 0x00000000 GPIO_A Function Select Register 1 GTSEL_A 0x0C R W 0x00000000 GPIO_A Function Select Registe...

Page 49: ...12 11 10 9 8 7 6 5 4 3 2 1 0 0 GS2 2 0 GS1 2 0 GS0 2 0 if a bit is set to 1 the corresponding GPIO pin is used by the other dedicated function blocks GSn 2 0 GPIO_A 10 8 GPIO_A 6 4 GPIO_A 2 0 Function...

Page 50: ...PIO_B 29 21 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 GPIO_B 9 7 0 GPIO_B 5 0 GPIO_B Direction Control Register GIOCON_B 0x80000314 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 GIO_B 29 21 0 15 1...

Page 51: ...unction Select 0 GPIO_B 8 pin is working as Normal GPIO Function 1 GPIO_B 8 UART TX signal of UART block NWE 7 GPIO_B 7 Function Select 0 GPIO_B 7 pin is working as Normal GPIO Function 1 GPIO_B 7 ND_...

Page 52: ...is working as Normal GPIO Function or I2S Data Output 1 GPIO_B 24 pin is working as EXTCLK from Clock Controller IDE 9 GPIO_B 9 Function Select 0 GPIO_B 9 pin is working as Normal GPIO Function or UAR...

Page 53: ...CHAPTER 7 CLOCK GENERATOR...

Page 54: ...unit that can manage several operating modes such as initialization mode normal operation mode idle mode stop mode The simple block diagram of clock generator is as followings WAITGEN XIN WAIT PLL PLL...

Page 55: ...er mode EXTCLK is used for external usage especially for CD application UTCLK is used as the main clock of UART controller These clocks are generated by 14bit DCO Digital Controlled Oscillator that ca...

Page 56: ...R W 0x00 TCLK Timer Control Register GCLKmode 0x28 R W 0x00 GCLK GSIO Control Register SW_nRST 0x3C R W 0x3FFF Software Reset for each peripherals Clock Control Register CKCTRL 0x80000400 31 30 29 28...

Page 57: ...e Timer block USB 6 USB Control 1 Disable USB block UART 5 UART Control 1 Disable UART block EXT 4 EXT Clock Control 1 Disable External Clock Output EXCLK pin CDC 2 CODEC Control 1 Disable internal CO...

Page 58: ...DIV1 18 Divisor Clock1 Select 0 Use Oscillator as DIVCLK1 1 Use PLL output as DIVCLK1 S M P PLL Frequency Setting S M P fPLL M 8 fXin P 2 2S The TCC720 has one PLL for generating of internal main cloc...

Page 59: ...reliable operation keep the n power of 2 relationships with divisor clock The target frequency can be acquired by writing the phase value calculated by the following equation to the PHASE register PH...

Page 60: ...CLK generator D_PHASE 13 0 DCLK Clock Frequency Select d 0 fDCLK fDIV d 214 0 fDCLK fDIV The divisor clock is selected by DIVD field of PLLmode register DCLK is also controlled by DAI bit of CKCTRL re...

Page 61: ...Clock Frequency Select e 0 fEXTCLK fDIV e 214 0 fEXTCLK fDIV The divisor clock is selected by DIVXT bit of EXTCLKmode EXTCLK is also controlled by EXT bit of CKCTRL register that can enable or disabl...

Page 62: ...pin as a divisor clock of UTCLK generator UT_PHASE 13 0 UTCLK Clock Frequency Select u 0 fUTCLK fDIV u 214 0 fUTCLK fDIV The divisor clock is selected by DIVUT bit of UTCLKmode UTCLK is also controll...

Page 63: ...HASE 26 fUBCLK fDIV UBCLK is also controlled by USB bit of CKCTRL register that can enable or disable UBCLK If this bit is set to low UBCLK is enabled and if it is high UBCLK is disabled DIVUB 9 8 UBC...

Page 64: ...19 18 17 16 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 DIVT 0 0 TC_PHASE 5 0 DIVT 9 8 TCLK Divisor Clock Select 0 use XIN pin as a divisor clock of TCLK generator 1 use PLL output as a divisor clock of...

Page 65: ...19 18 17 16 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 DIVG 0 0 GC_PHASE 5 0 DIVG 9 8 GCLK Divisor Clock Select 0 use XIN pin as a divisor clock of GCLK generator 1 use PLL output as a divisor clock of...

Page 66: ...Block is released 0 Reset for Miscellaneous Block is generated Miscellaneous block contains ADC and CODEC control register and leading zero counter register etc GS 6 GSIO Block Reset Control 1 Reset f...

Page 67: ...ec 16 2002 Preliminary Spec 0 51 7 14 IC 1 Interrupt Controller Block Reset Control 1 Reset for Interrupt Controller is released 0 Reset for Interrupt Controller is generated DAI 0 DAI CDIF Block Rese...

Page 68: ...CHAPTER 8 USB CONTROLLER...

Page 69: ...a transaction The endpoint EP0 has a single 16 byte FIFO Max packet size is 16 bytes And the endpoint EP1 and EP2 have a dual 128 byte FIFO respectively Max packet size of EP1 and EP2 is 64 bytes Ther...

Page 70: ...C Endpoint Interrupt Enable Register UBIEN 0x2C Interrupt Enable Register UBFRM1 0x30 Frame Number 1 Register UBFRM2 0x34 Frame Number 2 Register UBIDX 0x38 Index Register COMMON INDEXED REGISTER MAXP...

Page 71: ...bit whenever it updates the FADR field This bit is write only register FADR 6 0 Function Address n Function address This register maintains the USB Device Address assigned by the host The control prog...

Page 72: ...e Suspend Mode 1 R Indicates that the USB enters suspend mode ENSP 0 Type Enable Suspend Mode 0 R W Disable Suspend Mode 1 R W Enable Suspend Mode This register is used for suspend resume and reset si...

Page 73: ...ignaling RSM 1 Type Resume Interrupt Flag 1 R Indicates that the USB has received resume signaling in suspend mode SP 0 Type Suspend Interrupt Flag 1 R Indicates that the USB has received suspend sign...

Page 74: ...terrupt is generated under the following conditions For IN endpoints 1 IRDY field is cleared in the CSR register 2 FIFO is flushed 3 SENT STALL is set For OUT endpoints 1 ORDY field is set in the CSR...

Page 75: ...RRUPT ENABLE register except resume interrupt enable By default the USB reset interrupt is enabled If bit 0 the interrupt is disabled If bit 1 the interrupt is enabled Frame Number 1 Register UBFRM1 0...

Page 76: ...exed registers MAXP INCSR1 2 OCSR1 2 OFIFO1 2 The following registers denoted by suffix letter of n are index register Index register means that its address is shared by each end point blocks So if yo...

Page 77: ...FO Flush 1 R W IN FIFO is flushed 0 R This bit is cleared by the USB when the FIFO is flushed The interrupt is generated when this happens If a token is in progress the USB waits until the transmissio...

Page 78: ...it if it decodes an invalid token 0 W End the STALL condition CEND 4 Type Control Setup End 1 R Indicates that the control transfer ends before DEND bit is set 0 R Indicates that the CLSE is written b...

Page 79: ...Ready 0 R Indicates that the CLOR has been set to 1 1 R Indicates that a valid token is written to the FIFO IN CSR2 Register INCSR2n 0x80000548 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ASET ISO...

Page 80: ...shake 1 R W Start issuing a STALL Handshake 0 R W End the STALL Condition FLFF 4 Type Issue FIFO Flush 1 R W OUT FIFO is flushed 0 R W Stop flushing FIFO FFL 1 Type OUT FIFO Full 1 R Indicates that no...

Page 81: ...register OFIFO1n and OFIFO2n which maintain the write count OFIFO1n maintains the lower bytes while OFIFO2n maintains the higher byte When ORDY bit of OCSR1n is set for OUT endpoints these registers m...

Page 82: ...CHAPTER 9 UART IrDA CONTROLLER...

Page 83: ...FO Transmit FIFO IR Interrupt Generator Transmit Shift Receiver Shift RXD IREQ RZ code Modulator RZ code Demod IrDACFG2 IrDACFG1 Figure 9 1 UART Block Diagram This UART is simplified version of UART16...

Page 84: ...0 Name Address Type Reset Description RXD 0x00 R Receiver Buffer Register TXD 0x00 W Transmitter Holding Register DL 0x04 R W 0x0000 Divisor Latch Register IR 0x08 R W 0x000 Interrupt Register CR 0x0C...

Page 85: ...g When the transmission FIFO is not full writing of this register fills that data to transmission FIFO Checking TF flag of LSR register can monitor the status of a transmission FIFO Divisor Latch Regi...

Page 86: ...ceiver Data Available Interrupt 0 disabled 1 enabled FRS 2 Flag for Receiver Line Status Interrupt 0 Interrupt has not generated 1 Interrupt has generated but not cleared FTX 1 Flag for Transmitter Ho...

Page 87: ...Request for Transmitter Holding Register Empty Interrupt 0 Interrupt has not generated 1 Interrupt has generated but not cleared QRX 0 Request for Receiver Data Available Interrupt 0 Interrupt has not...

Page 88: ...ansmitted regardless of THR TF 7 Reset Transmitter FIFO 1 The transmitter FIFO is cleared RF 6 Reset Receiver FIFO 1 The receiver FIFO is cleared FIFO 5 4 RX FIFO Level Select n 0 1byte FIFO 1 2 byte...

Page 89: ...TCC720 UART IrDA 32 bit RISC Microprocessor for Digital Media Player Dec 16 2002 Preliminary Spec 0 51 9 7 ST 1 Stop Bit 0 1 Stop bit 1 2 Stop bit B7 0 Number of Bits per Character 0 8 bit 1 7 bit...

Page 90: ...mitter FIFO 0 Not empty 1 Empty Transmitter FIFO depth is fixed to 4 TF 3 Transmitter FIFO 0 Not full 1 Full Transmitter FIFO depth is fixed to 4 FE 2 Framing Status 0 Correct stop bit is received 1 T...

Page 91: ...de is used 1 IrDA TX is enabled P1 14 Transmit Pulse Type 0 Pulse width is proportional to selected baud speed 1 Pulse width is proportional to UART base clock speed POL 13 Transmit Pulse Polarity 0 T...

Page 92: ...to UART base clock speed POL 13 Receive Pulse Polarity 0 The polarity of received data is not inverted 1 The polarity of received data is inverted DEC 11 8 RX Data Decision Time n The decision point...

Page 93: ...CHAPTER 10 GSIO PORT...

Page 94: ...n be programmed using GSIO control field in the GSCR There are 5 control registers for GSIOs GSCR0 GSCR1 GSCR2 GSCR3 and GSICR The start time of transfer can be controlled with programming the delay c...

Page 95: ...ut Data Register GSCR2 0x28 R W GSIO2 Control Register GSDO3 0x30 R W GSIO3 Output Data Register GSDI3 0x34 R W GSIO3 Input Data Register GSCR3 0x38 R W GSIO3 Control Register GSIOn Output Data Regist...

Page 96: ...9 26 GSIO word size n GSIO data has n 1 bit unit n 0 15 WS 25 Word Size Select 0 GSIO word size is determined by WORD of GSCRn register 1 GSIO word size is determined by BW of GSDO register DIV 24 18...

Page 97: ...FRM SCK SDO output of GSIOn is come out from GPIO_B 23 21 If multiple bit of G 3 0 is set to 1 the output of each GSIO is orred and come out from GPIO_B 23 21 IEN 3 0 11 8 GSIO Interrupt Enable if bi...

Page 98: ...s 7 1 init_delay 2 clk_pol 0 frame_pol 1 frame1 18 frame2 20 last_clk_mask 0 1 0 2 3 4 5 6 7 8 9 10 D0 D1 D2 D3 14 15 16 D6 17 18 D7 19 20 PCLK base clk SDO SCK FRM clk_pol 1 1 0 2 3 4 5 6 7 8 9 10 D0...

Page 99: ...CHAPTER 11 MISCELLANEOUS PERIPHERALS...

Page 100: ...us operating option can be set by using ADCCON register it can convert up to 8 analog input and be operated as 10bit ADC at about 200ksps rates as well as 8bit ADC at about 250ksps rates It has standb...

Page 101: ...gister ADCDATA 0x80000A04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ADATA FLG ADATA 10 1 ADC Data adc When 8bit mode lsb 2bit must be ignored When 10bit...

Page 102: ...t Detection is disabled If the input data has the condition where the lower 4bits of the input data are DC and the remaining upper bits are all 0 or all 1 has continued 8192 cycles of LRCK 32fs then z...

Page 103: ...st be 256 fs 1 16KHz 22 05KHz mode System clock must be 512 fs 2 8KHz 11KHz mode System clock must be 512 fs RST 4 Reset Signal 0 ADC DAC reset is released 1 ADC DAC reset is generated DA 3 2 DAC Mode...

Page 104: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ADR DATA ADR 5 4 Gain Register Select 00 ADC Left Channel is selected 01 ADC Right Channel is selected 10 DAC Lef...

Page 105: ...the number of zero counting from MSB of X can be calculated by reading CLZ register If the value returned by reading CLZ register is Y the number of zero counting from MSB of X is 32 Y USB Port Contro...

Page 106: ...CHAPTER 12 DMA CONTROLLER...

Page 107: ...SMSK ST_DADR DINC DMSK C_DADR Address Calculator CH_CTRL Figure 12 1 DMA Controller Block Diagram There are various kinds of transfer modes for DMA operation The following table represents each type...

Page 108: ...ed as like as interrupt is generated Software type transfer SW_ARBIT SW_BURST means that the DMA transfer triggered by CHCTRL 0 flag enable flag When this flag is set to 1 the DMA transfer begins at t...

Page 109: ...ss of Destination Block HCOUNT 0x20 R W 0x00000000 Initial and Current Hop count CHCTRL 0x24 R W 0x00000000 Channel Configuration CLRDRQ 0x28 W Clear End of DMA flag Start Source Address Register ST_S...

Page 110: ...et to 1 the 27th bit of source address is masked and so on If a bit is masked a corresponding bit of address bus is unchanged during DMA transfer This function can be used to generate circular buffer...

Page 111: ...to 1 the 27th bit of source address is masked and so on If a bit is masked a corresponding bit of address bus is unchanged during DMA transfer This function can be used to generate circular buffer ad...

Page 112: ...21 20 19 18 17 16 C_DADR 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C_DADR 15 0 This register contains current destination address of DMA transfer HOP Count Register HCOUNT 0x80000E20 31 30 29 28 27...

Page 113: ...5 Issue Locked Transfer 0 DMA transfer begins from ST_SADR ST_DADR address 1 DMA transfer begins from C_SADR C_DADR address It must be used after the former transfer has been executed so that C_SADR a...

Page 114: ...nding enable bit in the interrupt controller must be set to 1 ahead CONT 1 Continuous Transfer 0 After all of hop transfer has executed the DMA channel is disabled 1 The DMA channel remains enabled so...

Page 115: ...CHAPTER 13 MEMORY CONTROLLER...

Page 116: ...rable data bus width through the GPIO pin or each configuration register The data bus width can be configured for each chip select separately The memory controller provide the power saving function fo...

Page 117: ...CSCFG0 0x10 R W 0x0B405601 External Chip Select 0 Configuration Register Initially set to SRAM CSCFG1 0x14 R W 0x0150569A External Chip Select 1 Configuration Register Initially set to IDE CSCFG2 0x1...

Page 118: ...AM controller is as the followings Refer to SDRAM cycle diagram in figure 13 2 SDRAM Configuration Register SDCFG 0xF0000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CL BW CW SDBASE RC RCD RD 2...

Page 119: ...K cycle is used to meet the read to precharge time RP 14 12 Delay of Precharge to Refresh tRP n n 1 number of HCLK cycle is used to meet the precharge to refresh time RW 11 RAS Width 0 12bit is used f...

Page 120: ...DQ0 DQ1 SDRAM Write Cycle Non sequential SDRAM Read Cycle Row Actived nCAS SDCLK nWE DQM DQM0 DQM1 DQ DQ0 DQ2 tCL DQM tCL SDRAM Precharge Refresh Cycle SDCLK SDnCS SDnCS nRAS SDnCS nWE nCAS tRP CAS1...

Page 121: ...mapped to these space as the system program including interrupt vector table is located in this area To satisfy this requirement TCC720 provide RM flag BM flag is used to select the boot procedure be...

Page 122: ...11 R The corresponding memory is configured by 8bit data bus bw is calculated by xoring the BW field of MCFG register and BW field of CSCFGn register that is bw BW of MCFG BW of CSCFGn BW of MCFG is...

Page 123: ...mory controller is always active regardless of request state unless power down or idle state begins RM 0 Type Remap Flag 0 The area 0 0x00000000 0x0FFFFFFF space is mapped to internal external boot RO...

Page 124: ...0 9 8 7 6 5 4 3 2 1 0 0 AMSK PSIZE CLADR STP PW HLD The reset value means the following configuration for each chip select Chip Select 0 16bit SRAM Base 0x40000000 tSTP 0 tPW 1 tHLD 1 Chip Select 1 32...

Page 125: ...s bit must be set to zero But if the system uses multiple NAND flashes by sharing a chip select but separating each data to 16 or 32bit data bus of TCC720 the AMSK must be set to 1 so the address can...

Page 126: ...DDR1 nOE tHLD tPW tH tPW DQRH nWE tSH ADDR0 SMEM_1 Type Cycle Bus width Data width ADDR1 nOE DQ1 tHLD tPW tH tSH tHLD tPW nCS XA DQM1 DQM0 DQ 15 8 DQ 7 0 DQ0 Figure 13 3 Basic Timing Diagram for Exter...

Page 127: ...se Command 0x70 Status Read Command status read command is generated by reading 0xM0000700 address not 0xM0000000 Refer to corresponding datasheet of NAND flash chip for detailed command list Linear A...

Page 128: ...7 6 5 4 3 2 1 0 Reserved IADDR When CPU writes to this register one cycle of address cycle is generated Data Register DATA 0xM0000010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA3 DATA2 15 14...

Page 129: ...s cleared to 0 In case of internal ROM the access speed is not enough to cope with that of system bus AHB So when the system bus clock is higher than about 40MHz the ROM access cycle must be extended...

Page 130: ...CHAPTER 14 BOOTING PROCEDURE...

Page 131: ...Table 14 1 Booting Mode of TCC720 BM Description 1 F W download from UART interface with XIN clock source 2 F W download from UART interface with XTIN clock source 3 NAND boot with non security NAND...

Page 132: ...al boot ROM When external boot mode the sequence begins from external ROM that is attached to nCS3 The bus width of external boot ROM can be determined by state of GPIO_A 5 4 at the rising edge of nRE...

Page 133: ...0xFF it is regarded as 0 and if 0xFF is received it is regarded as 1 So to receive 32bit value a host must transmit 32 bytes with MSB first order Figure 14 1 illustrates the transmission of one 32bit...

Page 134: ...f the transfer is succeeded or not v After all of codes are transferred TCC720 branches to address 0x00000000 This procedure is illustrated in figure 14 2 consist of 16 consequtive bytes transfer with...

Page 135: ...4 76 128M 512 128K 4 79 256M 2048 64K 5 AA DA At first TCC720 checks if the second byte of each spare area is 0xC4 or not starting from the last page to first page It considers the page of containing...

Page 136: ...ning from the initialization code In case of encrypted F W code it is decrypted and then copied to as like as in non encrypted case The next page number is consisted of 4 bytes and located at the size...

Page 137: ...4 bytes from NAND to SRAM JUMP to SRAM 0x00000000 Data 0xC4 No Yes N Register R0 N N 1 Encrypted Read SIZE 8 bytes from NAND Read the next page number N Yes No Read 2nd byte in spare data of page N In...

Page 138: ...pted mode the F W code in external flash is directly fetched to TCC720 without any other intermediate processing but in case of encrypted mode the F W code in external flash is stored in encrypted val...

Page 139: ...xFFFFFFFF Enabled Enabled Enabled Full Access 1 0x20000000 0x3FFFFFFF Enabled Disabled Enabled Full Access 2 0x40000000 0x4FFFFFFF Enabled Disabled Enabled Full Access 3 0x50000000 0x5FFFFFFF Enabled...

Page 140: ...CHAPTER 15 JTAG DEBUG INTERFACE...

Page 141: ...for developing the application programs It can be connected with Multi ICE of ARM or other third party s in circuit emulator supporting for ARM940T core With the use of in circuit emulator the user c...

Page 142: ...CHAPTER 16 PACKAGE DEMENSION...

Page 143: ...10 0 01 1 7 o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 53 54 55 56 57 58 59 60 61 62 63 64 52 51 50 49 46 47 48 45 44 43 42 41 40 39 36 37 38 35 34 33 10...

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