TeleChips TCC720, User Manual, Page: 116 / 143

TCC720
MEMORY CONTROLLER
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
13 - 1
13 MEMORY CONTROLLER
13.1 Overview
TCC720 has a memory controller for various kind of memory for digital media en-decoding
system. It can manipulate SDRAM, Flash (NAND, NOR type), ROM, SRAM type memories, and
also support the IDE interface for HDD or USB2.0 device. It has configurable data bus width
through the GPIO pin or each configuration register. The data bus width can be configured for
each chip select separately
The memory controller provide the power saving function for SDRAM (self refresh).
The following figure represents the block diagram of memory control unit.
SDRAM
Signal
Generator
Refresh
Controller
Memory
Control
Signals
AH
B
SDRAM
State
Machine
SDCFG
CSCFGn
ExtMEM
State
Machine
ExtMEM
Signal
Generator
Signal Mixer
Remap
Flag
Figure 13.1 Memory Controller Block Diagram
The registers for memory controller block have the base address of 0xF0000000.