TeleChips TCC720, User Manual

Page: 77 / 143

TCC720
USB CONTROLLER
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
8 - 9
IN CSR1 Register (INCSR1n) 0x80000544
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved -
CTGL STST ISST FLFF - FNE IRDY
CTGL
[6]
Type Clear Data Toggle Bit
1 W The data toggle bit is cleared
STST
[5]
Type STALL Handshake Issued
1 R Indicates that the STALL handshake is issued
0 W Clear by writing 0
ISST
[4]
Type Issue STALL Handshake
1 R/W Start issuing a STALL Handshake
0 R/W Clear to end STALL condition
FLFF
[3]
Type Issue FIFO Flush
1 R/W IN FIFO is flushed
0 R This bit is cleared by the USB when the FIFO is flushed. The
interrupt is generated when this happens. If a token is in
progress, the USB waits until the transmission is complete
before the FIFO is flushed. If two packets are loaded into the
FIFO, only the top-most packet (one that was intended to be
sent to the host) is flushed, and the corresponding IRDY bit for
that packet is cleared.
FNE
[1]
Type IN FIFO Not Empty
0 R/W Indicates that no packet of data is in IN-FIFO
1 R/W Indicates that at least one packet of data is in IN-FIFO
IRDY
[0]
Type IN Packet Ready
0 R Indicates that the packet has been successfully sent to host
1 W After writing a packet of data into the IN-FIFO, set this bit to 1.