TeleChips TCC720, User Manual

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TCC720
CLOCK GENERATOR
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
7 - 10
UBCLK (USB) Control Register (UBCLKmode) 0x8000041C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 DIVUB 0 0 UB_PHASE[5:0]
UBCLK is used as the main clock of USB block. It is generated by a DCO that has 6bit
resolution, and its frequency is set by writing the phase value calculated by the following
equation to the UB_PHASE register.
UB_PHASE = 2
6
* f
UBCLK
/ f
DIV
UBCLK is also controlled by USB bit of CKCTRL register that can enable or disable UBCLK. If
this bit is set to low, UBCLK is enabled and if it is high, UBCLK is disabled.
DIVUB
[9:8]
UBCLK Divisor Clock Select
0 use XIN pin as a divisor clock of UBCLK generator
1 use PLL output as a divisor clock of UBCLK generator
2, 3 use XTIN pin as a divisor clock of UBCLK generator
UB_PHASE
[5:0]
UBCLK Clock Frequency Select
ub (!= 0) f
UBCLK
= f
DIV
* ub / 2
6
0 f
UBCLK
= f
DIV
*)
The divisor clock is selected by DIVUB
bit of UBCLKmode
. UBCLK is also controlled by USB bit of
CKCTRL register that can enable or disable UBCLK. If this bit is set to high, UBCLK is disabled and if it is
low, UBCLK is enabled