TeleChips TCC720, User Manual

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TCC720
UART / IrDA
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
9 - 6
UART/IrDA Control Register (CR) 0x8000060C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 NO BK TF RF FIFO PR ST B7
NO
[9]
Start Bit Width Check
0 Check if the pulse width of start bit is more than 0.5 bit duration of baud rate
1 Don’t check the pulse width of start bit (used only for test or boot mode)
BK
[8]
Break Control Bit
0 Normal operation
1 Bit ‘0’ is transmitted regardless of THR
TF
[7]
Reset Transmitter FIFO
1 The transmitter FIFO is cleared
RF
[6]
Reset Receiver FIFO
1 The receiver FIFO is cleared
FIFO
[5:4]
RX FIFO Level Select
n 0 = 1byte FIFO, 1 = 2 byte FIFO
2 = 4 byte FIFO, 3 = 7 byte FIFO
*) This field controls the RDA(Receive Data Available) flag or interrupt only, that is the actual
FIFO depth can’t be modified and fixed to 8. If this field is set to 1, it means that the RDA flag or
interrupt is influenced when the number of received data in the RX FIFO is 2. It is recommended
that this field is set to 0, so right after reception of some data, the RDA flag or interrupt can be
generated.
PR
[3:2]
Parity Bit Select
0 Even parity
1 Odd parity
2, 3 Parity is disabled