TeleChips TCC720, User Manual, Page: 60 / 143

TCC720
CLOCK GENERATOR
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
7 - 7
DCLK (DAI/CODEC) Control Register (DCLKmode) 0x8000040C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIVD
D_PHASE[13:0]
DIVD
[15:14]
DCLK Divisor Clock Select
0 use XIN as a divisor clock of DCLK generator
1 use PLL output as a divisor clock of DCLK generator
2, 3 use XTIN pin as a divisor clock of DCLK generator
D_PHASE
[13:0]
DCLK Clock Frequency Select
d (!= 0) f
DCLK
= f
DIV
* d / 2
14
0 f
DCLK
= f
DIV
*) The divisor clock is selected by DIVD field of PLLmode register.
DCLK is also controlled by DAI
bit of CKCTRL register that can enable or disable DCLK. If this bit is set to high, DCLK is disabled and if it
is low, DCLK is enabled.
DCLK is for DAI and internal CODEC requires 512*fs frequency. To make DCLK of this
frequency, first set the frequency of PLL (f
DIV
) more higher than 512*fs and set D_PHASE
according to the above formulae. It is recommended to set the frequency of PLL by the n power
of 2, than the duty ratio of DCLK is only dependant of that of PLL clock.