TeleChips TCC720, User Manual

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TCC720
ADDRESS & REGISTER MAP
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
2 - 2
detailed operation.
TCC720 has only one chip select for SDRAM, so its address space is dependent on SDRAM
size attached to TCC720.
TCC720 has various peripherals for controlling a digital audio en-decoder system. These
peripherals can be configured appropriately by it’s own registers that can be accessed through
specially allocated address. These address maps are represented in the following table. In case
of memory controller, its space is separated for preventing illegal accessing.
Refer to corresponding sections for detail information of each peripheral.
Table 2.2 Address Allocation for Internal Peripherals (Base Address = 0x80000000)
Offset Address Space Peripheral
0x000 ~ 0x0FF DAI & CDIF
0x100 ~ 0x1FF Interrupt Controller
0x200 ~ 0x2FF Timer Counter
0x300 ~ 0x3FF GPIO
0x400 ~ 0x4FF Clock Generator & Power Management
0x500 ~ 0x5FF USB Function
0x600 ~ 0x6FF UART/IrDA
0x700 ~ 0x7FF GSIO (General Purpose Serial Input/Output)
0x800 ~ 0x8FF -
0x900 ~ 0x9FF -
0xA00 ~ 0xAFF Analog Control & Etc.
0xB00 ~ 0xBFF -
0xC00 ~ 0xCFF -
0xD00 ~ 0xDFF -
0xE00 ~ 0xEFF DMA Controller
0xF00 ~ 0xFFF -
*) Address decoding logic only monitors base address (i.e. 0x8xxxxxxx), and bit11~bit8 of
accessing address bus. So care must be taken not to modify these registers unintentionally.